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Allocate fewer registers and tighten up alignment restrictions.
llvm-svn: 17929
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cc4074987b
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@ -25,13 +25,20 @@ include "../SparcRegisterInfo.td"
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//
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def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5,
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G1, G2, G3, G4, G5, G6, G7,
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G1,
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O0, O1, O2, O3, O4, O5, O7,
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// Non-allocatable regs
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O6, I6, I7, G0]> {
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// Non-allocatable regs:
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G2, G3, G4, // FIXME: OK for use only in
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// applications, not libraries.
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O6, // stack ptr
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I6, // frame ptr
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I7, // return address
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G0, // constant zero
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G5, G6, G7 // reserved for kernel
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]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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return end()-4; // Don't allocate special registers
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return end()-10; // Don't allocate special registers
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}
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}];
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}
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@ -31,7 +31,7 @@ namespace {
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///
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SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
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IntrinsicLowering *IL)
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: TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8),
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: TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8, 4, 4, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) {
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}
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