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Don't forget subreg indices when folding load / store.
llvm-svn: 85048
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parent
859d9f3b07
commit
77ecc0adc5
@ -750,18 +750,24 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned SrcSubReg = MI->getOperand(1).getSubReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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if (Opc == ARM::MOVr)
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addReg(SrcReg,
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getKillRegState(isKill) | getUndefRegState(isUndef),
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SrcSubReg)
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.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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else // ARM::t2MOVr
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addReg(SrcReg,
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getKillRegState(isKill) | getUndefRegState(isUndef),
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SrcSubReg)
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned DstSubReg = MI->getOperand(0).getSubReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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if (Opc == ARM::MOVr)
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@ -769,14 +775,14 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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getUndefRegState(isUndef), DstSubReg)
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.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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else // ARM::t2MOVr
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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getUndefRegState(isUndef), DstSubReg)
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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}
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} else if (Opc == ARM::tMOVgpr2gpr ||
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@ -784,20 +790,25 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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Opc == ARM::tMOVgpr2tgpr) {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned SrcSubReg = MI->getOperand(1).getSubReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addReg(SrcReg,
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getKillRegState(isKill) | getUndefRegState(isUndef),
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SrcSubReg)
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.addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned DstSubReg = MI->getOperand(0).getSubReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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getUndefRegState(isUndef),
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DstSubReg)
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.addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
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}
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} else if (Opc == ARM::FCPYS) {
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@ -805,21 +816,25 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned SrcSubReg = MI->getOperand(1).getSubReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
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SrcSubReg)
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.addFrameIndex(FI)
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.addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned DstSubReg = MI->getOperand(0).getSubReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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getUndefRegState(isUndef),
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DstSubReg)
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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}
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}
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@ -828,20 +843,25 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned SrcSubReg = MI->getOperand(1).getSubReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addReg(SrcReg,
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getKillRegState(isKill) | getUndefRegState(isUndef),
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SrcSubReg)
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned DstSubReg = MI->getOperand(0).getSubReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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getUndefRegState(isUndef),
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DstSubReg)
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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}
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}
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