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https://github.com/RPCS3/llvm-mirror.git
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Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty llvm-svn: 21222
This commit is contained in:
Nate Begeman
parent
d2ae9221c7
commit
783fe2108e
@ -473,7 +473,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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}
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namespace {
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Statistic<>Rotates("ppc-codegen", "Number of rotates emitted");
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Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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@ -492,7 +492,7 @@ class ISel : public SelectionDAGISel {
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unsigned GlobalBaseReg;
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bool GlobalBaseInitialized;
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bool RecordSuccess;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
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ISelDAG(0) {}
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@ -526,7 +526,7 @@ public:
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unsigned getConstDouble(double floatVal, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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unsigned SelectSetCR0(SDOperand CC);
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExpr(SDOperand N, bool Recording=false);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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@ -648,6 +648,17 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
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return 0;
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}
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/// NodeHasRecordingVariant - If SelectExpr can always produce code for
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/// NodeOpcode that also sets CR0 as a side effect, return true. Otherwise,
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/// return false.
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static bool NodeHasRecordingVariant(unsigned NodeOpcode) {
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switch(NodeOpcode) {
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default: return false;
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case ISD::AND:
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case ISD::OR: return true;
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}
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}
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/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
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/// to Condition. If the Condition is unordered or unsigned, the bool argument
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/// U is set to true, otherwise it is set to false.
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@ -684,6 +695,8 @@ static unsigned IndexedOpForOp(unsigned Opcode) {
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return 0;
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}
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///
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// Structure used to return the necessary information to codegen an SDIV as
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// a multiply.
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struct ms {
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@ -927,7 +940,6 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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// where both bitfield halves are sourced from the same value.
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if (IsRotate &&
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OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
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++Rotates; // Statistic
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Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
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.addImm(0).addImm(31);
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@ -955,13 +967,29 @@ unsigned ISel::SelectSetCR0(SDOperand CC) {
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SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
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if (SetCC && CC.getOpcode() == ISD::SETCC) {
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bool U;
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bool AlreadySelected = false;
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Opc = getBCCForSetCC(SetCC->getCondition(), U);
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Tmp1 = SelectExpr(SetCC->getOperand(0));
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// Pass the optional argument U to getImmediateForOpcode for SETCC,
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// so that it knows whether the SETCC immediate range is signed or not.
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if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
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Tmp2, U)) {
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// For comparisons against zero, we can implicity set CR0 if a recording
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// variant (e.g. 'or.' instead of 'or') of the instruction that defines
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// operand zero of the SetCC node is available.
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if (0 == Tmp2 &&
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NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode())) {
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RecordSuccess = false;
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Tmp1 = SelectExpr(SetCC->getOperand(0), true);
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if (RecordSuccess) {
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++Recorded;
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return Opc;
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}
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AlreadySelected = true;
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}
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// If we could not implicitly set CR0, then emit a compare immediate
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// instead.
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if (!AlreadySelected) Tmp1 = SelectExpr(SetCC->getOperand(0));
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
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else
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@ -969,6 +997,7 @@ unsigned ISel::SelectSetCR0(SDOperand CC) {
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} else {
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bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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Tmp1 = SelectExpr(SetCC->getOperand(0));
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Tmp2 = SelectExpr(SetCC->getOperand(1));
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BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
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}
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@ -1337,7 +1366,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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return 0;
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}
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unsigned ISel::SelectExpr(SDOperand N) {
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unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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unsigned Result;
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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@ -1588,10 +1617,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp1 = SelectExpr(N.getOperand(0));
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switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
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default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
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case MVT::i16:
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case MVT::i16:
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BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
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break;
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case MVT::i8:
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case MVT::i8:
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BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
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break;
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case MVT::i1:
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@ -1681,7 +1710,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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default: assert(0 && "unhandled result code");
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case 0: // No immediate
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
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Opc = Recording ? PPC::ANDo : PPC::AND;
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case 1: // Low immediate
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BuildMI(BB, PPC::ANDIo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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@ -1690,6 +1720,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, PPC::ANDISo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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}
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RecordSuccess = true;
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return Result;
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case ISD::OR:
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@ -1700,7 +1731,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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default: assert(0 && "unhandled result code");
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case 0: // No immediate
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp2);
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Opc = Recording ? PPC::ORo : PPC::OR;
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RecordSuccess = true;
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case 1: // Low immediate
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BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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@ -140,12 +140,14 @@ def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)">;
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}
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let Defs = [CR0] in {
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def ANDIo : DForm_4<28, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2">;
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def ANDISo : DForm_4<29, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2">;
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}
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def ORI : DForm_4<24, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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@ -222,6 +224,9 @@ def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
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def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB">;
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let Defs = [CR0] in
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def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">;
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def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB">;
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def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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