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This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
This commit is contained in:
Vladimir Medic
parent
cc66f54baf
commit
78876a9ef9
@ -479,6 +479,17 @@ class TEQ_FM<bits<6> funct> {
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let Inst{5-0} = funct;
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}
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class TEQI_FM<bits<5> funct> {
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bits<5> rs;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = 1;
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let Inst{25-21} = rs;
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let Inst{20-16} = funct;
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let Inst{15-0} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// System calls format <op|code_|funct>
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//===----------------------------------------------------------------------===//
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@ -630,6 +630,9 @@ class TEQ_FT<string opstr, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
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!strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
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class TEQI_FT<string opstr, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
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!strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
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// Mul, Div
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class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
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list<Register> DefRegs> :
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@ -914,6 +917,18 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
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def SYNC : SYNC_FT, SYNC_FM;
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def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
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def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
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def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
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def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
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def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
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def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
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def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
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def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
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def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
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def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
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def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
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def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
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def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
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def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
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@ -1093,6 +1108,13 @@ def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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def : InstAlias<"break", (BREAK 0, 0), 1>;
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def : InstAlias<"ei", (EI ZERO), 1>;
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def : InstAlias<"di", (DI ZERO), 1>;
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def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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@ -1,7 +1,7 @@
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# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
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# RUN: FileCheck -check-prefix=CHECK32 %s
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# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips64r2 | \
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# RUN: FileCheck -check-prefix=CHECK64 %s
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# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 \
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# RUN: | FileCheck -check-prefix=CHECK64 %s
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# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
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# CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
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@ -17,6 +17,24 @@
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# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
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# CHECK32: wait # encoding: [0x42,0x00,0x00,0x20]
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# CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
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# CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
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# CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
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# CHECK32: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
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# CHECK32: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
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# CHECK32: tgei $3, 3 # encoding: [0x04,0x68,0x00,0x03]
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# CHECK32: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
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# CHECK32: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
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# CHECK32: tgeiu $3, 7 # encoding: [0x04,0x69,0x00,0x07]
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# CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
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# CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
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# CHECK32: tlti $3, 31 # encoding: [0x04,0x6a,0x00,0x1f]
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# CHECK32: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
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# CHECK32: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3]
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# CHECK32: tltiu $3, 255 # encoding: [0x04,0x6b,0x00,0xff]
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# CHECK32: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
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# CHECK32: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
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# CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
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# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
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# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
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@ -32,6 +50,25 @@
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# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
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# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
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# CHECK64: wait # encoding: [0x42,0x00,0x00,0x20]
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# CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
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# CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
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# CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
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# CHECK64: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
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# CHECK64: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
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# CHECK64: tgei $3, 3 # encoding: [0x04,0x68,0x00,0x03]
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# CHECK64: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
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# CHECK64: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
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# CHECK64: tgeiu $3, 7 # encoding: [0x04,0x69,0x00,0x07]
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# CHECK64: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
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# CHECK64: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
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# CHECK64: tlti $3, 31 # encoding: [0x04,0x6a,0x00,0x1f]
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# CHECK64: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
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# CHECK64: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3]
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# CHECK64: tltiu $3, 255 # encoding: [0x04,0x6b,0x00,0xff]
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# CHECK64: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
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# CHECK64: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
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# CHECK64: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
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break
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break 7
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break 7,5
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@ -48,3 +85,22 @@
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ei $10
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wait
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teq $0,$3
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teq $0,$3,1
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teqi $3,1
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tge $0,$3
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tge $0,$3,3
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tgei $3,3
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tgeu $0,$3
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tgeu $0,$3,7
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tgeiu $3,7
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tlt $0,$3
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tlt $0,$3,31
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tlti $3,31
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tltu $0,$3
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tltu $0,$3,255
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tltiu $3,255
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tne $0,$3
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tne $0,$3,1023
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tnei $3,1023
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