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Clear the llvm release notes to make room for 3.6.
llvm-svn: 216292
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Rafael Espindola
parent
fea5664211
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78ec7d3e35
@ -6,8 +6,8 @@ LLVM 3.5 Release Notes
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:local:
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.. warning::
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These are in-progress notes for the upcoming LLVM 3.5 release. You may
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prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
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These are in-progress notes for the upcoming LLVM 3.6 release. You may
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prefer the `LLVM 3.5 Release Notes <http://llvm.org/releases/3.5/docs
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/ReleaseNotes.html>`_.
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@ -15,7 +15,7 @@ Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 3.5. Here we describe the status of LLVM, including major improvements
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release 3.6. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <http://llvm.org/releases/>`_.
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@ -34,37 +34,6 @@ page <http://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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* All backends have been changed to use the MC asm printer and support for the
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non MC one has been removed.
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* Clang can now successfully self-host itself on Linux/Sparc64 and on
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FreeBSD/Sparc64.
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* LLVM now assumes the assembler supports ``.loc`` for generating debug line
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numbers. The old support for printing the debug line info directly was only
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used by ``llc`` and has been removed.
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* All inline assembly is parsed by the integrated assembler when it is enabled.
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Previously this was only the case for object-file output. It is now the case
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for assembly output as well. The integrated assembler can be disabled with
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the ``-no-integrated-as`` option.
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* llvm-ar now handles IR files like regular object files. In particular, a
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regular symbol table is created for symbols defined in IR files, including
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those in file scope inline assembly.
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* LLVM now always uses cfi directives for producing most stack
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unwinding information.
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* The prefix for loop vectorizer hint metadata has been changed from
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``llvm.vectorizer`` to ``llvm.loop.vectorize``. In addition,
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``llvm.vectorizer.unroll`` metadata has been renamed
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``llvm.loop.interleave.count``.
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* Some backends previously implemented Atomic NAND(x,y) as ``x & ~y``. Now
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all backends implement it as ``~(x & y)``, matching the semantics of GCC 4.4
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and later.
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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@ -87,138 +56,27 @@ Non-comprehensive list of changes in this release
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Changes to the ARM Backend
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--------------------------
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Since release 3.3, a lot of new features have been included in the ARM
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back-end but weren't production ready (ie. well tested) on release 3.4.
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Just after the 3.4 release, we started heavily testing two major parts
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of the back-end: the integrated assembler (IAS) and the ARM exception
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handling (EHABI), and now they are enabled by default on LLVM/Clang.
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During this release ...
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The IAS received a lot of GNU extensions and directives, as well as some
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specific pre-UAL instructions. Not all remaining directives will be
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implemented, as we made judgement calls on the need versus the complexity,
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and have chosen simplicity and future compatibility where hard decisions
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had to be made. The major difference is, as stated above, the IAS validates
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all inline ASM, not just for object emission, and that cause trouble with
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some uses of inline ASM as pre-processor magic.
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So, while the IAS is good enough to compile large projects (including most
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of the Linux kernel), there are a few things that we can't (and probably
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won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
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Exception handling is another big change. After extensive testing and
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changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
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The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
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which were used to enable EHABI in the previous releases, are removed now.
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This means all ARM code will emit EH unwind tables, or CFI unwinding (for
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debug/profiling), or both. To avoid run-time inconsistencies, C code will
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also emit EH tables (in case they interoperate with C++ code), as is the
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case for other architectures (ex. x86_64).
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Changes to the MIPS Target
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--------------------------
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There has been a large amount of improvements to the MIPS target which can be
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broken down into subtarget, ABI, and Integrated Assembler changes.
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Subtargets
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^^^^^^^^^^
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Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6
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and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32
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and MIPS64 architectures. For example, FPU registers are always 64-bits wide,
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FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions
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(such as lwl and lwr) have been replaced with a requirement for ordinary memory
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operations to support unaligned operations. Full details of MIPS32 and MIPS64
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Release 6 can be found on the `MIPS64 Architecture page at Imagination
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Technologies <http://www.imgtec.com/mips/architectures/mips64.asp>`_.
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This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium
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Octeon CPU's.
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Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA
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on MIPS64.
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Support for IEEE 754 (2008) NaN values has been added.
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ABI and ABI extensions
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^^^^^^^^^^^^^^^^^^^^^^
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There has also been considerable ABI work since the 3.4 release. This release
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adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI
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Extension, and the O32-FP64A ABI Extension.
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The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a
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64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the
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default 64-bit ABI in LLVM. This differs from GCC where N32 is the default
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64-bit ABI.
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The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64
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ABI Extension and may be linked with either but may not be linked with both of
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these simultaneously. It extends the O32 ABI to allow the same code to execute
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without modification on processors with 32-bit FPU registers as well as 64-bit
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FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI
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on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with
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-mfpxx. It is expected that future releases of LLVM will enable the FPXX
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Extension for O32 on all triples.
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The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU's
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with 64-bit registers and is enabled with -mfp64. This replaces an undocumented
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and unsupported O32 extension which was previously enabled with -mfp64. It is
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100% compatible with the O32-FPXX ABI Extension.
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The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension
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which allows interlinking with unmodified binaries that use the base O32 ABI.
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Integrated Assembler
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^^^^^^^^^^^^^^^^^^^^
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The MIPS Integrated Assembler has undergone a substantial overhaul including a
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rewrite of the assembly parser. It's not ready for general use in this release
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but adventurous users may wish to enable it using ``-fintegrated-as``.
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In this release, the integrated assembler supports the majority of MIPS-I,
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MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64,
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MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions
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such as MSA. It also supports several of the MIPS specific assembler directives
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such as ``.set``, ``.module``, ``.cpload``, etc.
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During this release ...
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Changes to the PowerPC Target
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-----------------------------
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The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
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now fully supported. This includes support for the Altivec instruction set.
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During this release ...
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The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
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is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI
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for Big Endian. Currently, it is not possible to override these defaults.
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That capability will be available (albeit not recommended) in a future release.
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Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
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specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
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Efforts are underway to move this to a location that doesn't require
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registration, but the planned site isn't ready yet.
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Experimental support for the VSX instruction set introduced with ISA 2.06
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is now available using the ``-mvsx`` switch. Work remains on this, so it
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is not recommended for production use. VSX is disabled for Little Endian
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regardless of this switch setting.
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Load/store cost estimates have been improved.
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Constant hoisting has been enabled.
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Global named register support has been enabled.
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Initial support for PIC code has been added for the 32-bit ELF subtarget.
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Further support will be available in a future release.
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External Open Source Projects Using LLVM 3.5
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External Open Source Projects Using LLVM 3.6
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============================================
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An exciting aspect of LLVM is that it is used as an enabling technology for
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a lot of other language and tools projects. This section lists some of the
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projects that have already been updated to work with LLVM 3.5.
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projects that have already been updated to work with LLVM 3.6.
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* A project
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Additional Information
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