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Fix encoding for compares. No Rd register.

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llvm-svn: 116414
This commit is contained in:
Jim Grosbach 2010-10-13 18:05:25 +00:00
parent 9c4a598ef2
commit 79156dadf2
1 changed files with 3 additions and 6 deletions
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9
lib/Target/ARM/ARMInstrInfo.td
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@ -569,11 +569,10 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
opc, "\t$Rn, $imm",
[(opnode GPR:$Rn, so_imm:$imm)]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{15-12} = Rd;
let Inst{15-12} = 0b0000;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
let Inst{20} = 1;
@ -582,26 +581,24 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
opc, "\t$Rn, $Rm",
[(opnode GPR:$Rn, GPR:$Rm)]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let isCommutable = Commutable;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{15-12} = 0b0000;
let Inst{19-16} = Rn;
let Inst{20} = 1;
}
def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
opc, "\t$Rn, $shift",
[(opnode GPR:$Rn, so_reg:$shift)]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{15-12} = 0b0000;
let Inst{19-16} = Rn;
let Inst{20} = 1;
}