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AMDGPU: Make i64 loads/stores promote to v2i32
Now that unaligned access expansion should not attempt to produce i64 accesses, we can remove the hack in PreprocessISelDAG where this is done. This allows splitting i64 private accesses while allowing the new add nodes indexing the vector components can be folded with the base pointer arithmetic. llvm-svn: 268293
This commit is contained in:
Matt Arsenault
parent
b357c876ed
commit
7932e530a0
@ -1586,61 +1586,6 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
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}
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}
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}
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// XXX - Other targets seem to be able to do this without a worklist.
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SmallVector<LoadSDNode *, 8> LoadsToReplace;
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SmallVector<StoreSDNode *, 8> StoresToReplace;
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for (SDNode &Node : CurDAG->allnodes()) {
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(&Node)) {
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EVT VT = LD->getValueType(0);
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if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
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continue;
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// To simplify the TableGen patters, we replace all i64 loads with v2i32
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// loads. Alternatively, we could promote i64 loads to v2i32 during DAG
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// legalization, however, so places (ExpandUnalignedLoad) in the DAG
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// legalizer assume that if i64 is legal, so doing this promotion early
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// can cause problems.
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LoadsToReplace.push_back(LD);
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} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(&Node)) {
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// Handle i64 stores here for the same reason mentioned above for loads.
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SDValue Value = ST->getValue();
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if (Value.getValueType() != MVT::i64 || ST->isTruncatingStore())
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continue;
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StoresToReplace.push_back(ST);
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}
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}
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for (LoadSDNode *LD : LoadsToReplace) {
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SDLoc SL(LD);
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SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SL, LD->getChain(),
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LD->getBasePtr(), LD->getMemOperand());
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SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SL,
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MVT::i64, NewLoad);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLoad.getValue(1));
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(LD, 0), BitCast);
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Modified = true;
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}
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for (StoreSDNode *ST : StoresToReplace) {
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SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(ST),
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MVT::v2i32, ST->getValue());
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const SDValue StoreOps[] = {
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ST->getChain(),
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NewValue,
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ST->getBasePtr(),
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ST->getOffset()
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};
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CurDAG->UpdateNodeOperands(ST, StoreOps);
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Modified = true;
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}
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// XXX - Is this necessary?
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if (Modified)
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CurDAG->RemoveDeadNodes();
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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@ -95,12 +95,24 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
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setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
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setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
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setOperationAction(ISD::LOAD, MVT::f64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::i64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
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setOperationAction(ISD::STORE, MVT::v8i32, Custom);
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setOperationAction(ISD::STORE, MVT::v16i32, Custom);
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setOperationAction(ISD::STORE, MVT::i1, Custom);
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setOperationAction(ISD::STORE, MVT::v4i32, Custom);
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setOperationAction(ISD::STORE, MVT::f64, Promote);
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AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
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setOperationAction(ISD::STORE, MVT::i64, Promote);
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AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
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setOperationAction(ISD::SELECT, MVT::i64, Custom);
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setOperationAction(ISD::SELECT, MVT::f64, Promote);
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AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
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@ -14,7 +14,7 @@ define void @materialize_0_i32(i32 addrspace(1)* %out) {
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; GCN-LABEL: {{^}}materialize_0_i64:
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; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_0_i64(i64 addrspace(1)* %out) {
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store i64 0, i64 addrspace(1)* %out
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@ -31,7 +31,7 @@ define void @materialize_neg1_i32(i32 addrspace(1)* %out) {
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; GCN-LABEL: {{^}}materialize_neg1_i64:
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; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], -1{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_neg1_i64(i64 addrspace(1)* %out) {
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store i64 -1, i64 addrspace(1)* %out
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@ -172,7 +172,7 @@ define void @s_test_canonicalize_var_f64(double addrspace(1)* %out, double %val)
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; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f64:
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; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @test_fold_canonicalize_p0_f64(double addrspace(1)* %out) #1 {
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%canonicalized = call double @llvm.canonicalize.f64(double 0.0)
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@ -225,7 +225,7 @@ define void @test_fold_canonicalize_literal_f64(double addrspace(1)* %out) #1 {
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; DENORM-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xfffff{{$}}
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; NODENORM: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; NODENORM: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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; NODENORM: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @test_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #1 {
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%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double))
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@ -238,7 +238,7 @@ define void @test_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #1
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; DENORM-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x800fffff{{$}}
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; NODENORM: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; NODENORM: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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; NODENORM: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @test_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #1 {
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%canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double))
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@ -510,7 +510,7 @@ define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
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; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64:
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; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
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; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0
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; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], v[[LO_VREG]]{{$}}
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; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
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define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
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store double 0.0, double addrspace(1)* %out
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@ -4,12 +4,11 @@
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; GCN-LABEL: {{^}}v_uextract_bit_31_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO1]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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@ -27,12 +26,11 @@ define void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)*
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; GCN-LABEL: {{^}}v_uextract_bit_63_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO1]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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@ -50,12 +48,11 @@ define void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)*
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; GCN-LABEL: {{^}}v_uextract_bit_95_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO1]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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@ -73,12 +70,11 @@ define void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)*
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; GCN-LABEL: {{^}}v_uextract_bit_127_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO1]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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