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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 12:43:36 +01:00
[MIPS GlobalISel] Select 4 byte unaligned load and store
Improve legality checks for load and store, 4 byte scalar load and store are now legal for all subtargets. During regbank selection 4 byte unaligned loads and stores for MIPS32r5 and older get mapped to gprb. Select 4 byte unaligned loads and stores for MIPS32r5. Fix tests that unintentionally had unaligned load or store. Differential Revision: https://reviews.llvm.org/D74624
This commit is contained in:
Petar Avramovic
parent
476c0607dd
commit
7933e40c35
@ -49,6 +49,12 @@ private:
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getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
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unsigned selectLoadStoreOpCode(MachineInstr &I,
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MachineRegisterInfo &MRI) const;
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bool buildUnalignedStore(MachineInstr &I, unsigned Opc,
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MachineOperand &BaseAddr, unsigned Offset,
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MachineMemOperand *MMO) const;
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bool buildUnalignedLoad(MachineInstr &I, unsigned Opc, Register Dest,
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MachineOperand &BaseAddr, unsigned Offset,
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Register TiedDest, MachineMemOperand *MMO) const;
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const MipsTargetMachine &TM;
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const MipsSubtarget &STI;
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@ -248,6 +254,35 @@ MipsInstructionSelector::selectLoadStoreOpCode(MachineInstr &I,
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return Opc;
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}
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bool MipsInstructionSelector::buildUnalignedStore(
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MachineInstr &I, unsigned Opc, MachineOperand &BaseAddr, unsigned Offset,
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MachineMemOperand *MMO) const {
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MachineInstr *NewInst =
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
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.add(I.getOperand(0))
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.add(BaseAddr)
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.addImm(Offset)
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.addMemOperand(MMO);
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if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
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return false;
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return true;
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}
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bool MipsInstructionSelector::buildUnalignedLoad(
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MachineInstr &I, unsigned Opc, Register Dest, MachineOperand &BaseAddr,
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unsigned Offset, Register TiedDest, MachineMemOperand *MMO) const {
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MachineInstr *NewInst =
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
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.addDef(Dest)
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.add(BaseAddr)
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.addImm(Offset)
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.addUse(TiedDest)
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.addMemOperand(*I.memoperands_begin());
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if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
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return false;
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return true;
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}
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bool MipsInstructionSelector::select(MachineInstr &I) {
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MachineBasicBlock &MBB = *I.getParent();
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@ -404,10 +439,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
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case G_LOAD:
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case G_ZEXTLOAD:
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case G_SEXTLOAD: {
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const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);
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if (NewOpc == I.getOpcode())
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return false;
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auto MMO = *I.memoperands_begin();
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MachineOperand BaseAddr = I.getOperand(1);
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int64_t SignedOffset = 0;
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// Try to fold load/store + G_PTR_ADD + G_CONSTANT
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@ -429,11 +461,48 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
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}
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}
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// Unaligned memory access
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if (MMO->getSize() > MMO->getAlignment() &&
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!STI.systemSupportsUnalignedAccess()) {
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if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI))
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return false;
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if (I.getOpcode() == G_STORE) {
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if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO))
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return false;
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if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO))
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return false;
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I.eraseFromParent();
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return true;
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}
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if (I.getOpcode() == G_LOAD) {
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Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
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.addDef(ImplDef);
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Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,
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ImplDef, MMO))
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return false;
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if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(),
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BaseAddr, SignedOffset, Tmp, MMO))
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return false;
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I.eraseFromParent();
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return true;
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}
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return false;
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}
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const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);
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if (NewOpc == I.getOpcode())
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return false;
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
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.add(I.getOperand(0))
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.add(BaseAddr)
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.addImm(SignedOffset)
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.addMemOperand(*I.memoperands_begin());
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.addMemOperand(MMO);
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break;
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}
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case G_UDIV:
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@ -21,22 +21,38 @@ struct TypesAndMemOps {
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LLT ValTy;
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LLT PtrTy;
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unsigned MemSize;
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bool MustBeNaturallyAligned;
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bool SystemSupportsUnalignedAccess;
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};
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// Assumes power of 2 memory size. Subtargets that have only naturally-aligned
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// memory access need to perform additional legalization here.
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bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
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assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size");
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assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align");
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if (MemSize > AlignInBits)
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return true;
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return false;
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}
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static bool
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CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
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std::initializer_list<TypesAndMemOps> SupportedValues) {
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unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits;
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// Non power of two memory access is never legal.
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if (!isPowerOf2_64(QueryMemSize))
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return false;
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for (auto &Val : SupportedValues) {
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if (Val.ValTy != Query.Types[0])
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continue;
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if (Val.PtrTy != Query.Types[1])
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continue;
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if (Val.MemSize != Query.MMODescrs[0].SizeInBits)
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continue;
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if (Val.MustBeNaturallyAligned &&
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Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
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if (Val.MemSize != QueryMemSize)
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continue;
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if (!Val.SystemSupportsUnalignedAccess &&
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isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits))
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return false;
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return true;
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}
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return false;
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@ -79,19 +95,27 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.legalFor({s32})
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.maxScalar(0, s32);
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// MIPS32r6 does not have alignment restrictions for memory access.
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// For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned
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// to at least a multiple of its own size. There is however a two instruction
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// combination that performs 4 byte unaligned access (lwr/lwl and swl/swr)
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// therefore 4 byte load and store are legal and will use NoAlignRequirements.
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bool NoAlignRequirements = true;
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},
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{s32, p0, 16, ST.hasMips32r6()},
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{s32, p0, 32, ST.hasMips32r6()},
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{p0, p0, 32, ST.hasMips32r6()},
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{s64, p0, 64, ST.hasMips32r6()}}))
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if (CheckTy0Ty1MemSizeAlign(
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Query, {{s32, p0, 8, NoAlignRequirements},
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{s32, p0, 16, ST.systemSupportsUnalignedAccess()},
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{s32, p0, 32, NoAlignRequirements},
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{p0, p0, 32, NoAlignRequirements},
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{s64, p0, 64, ST.systemSupportsUnalignedAccess()}}))
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return true;
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if (ST.hasMSA() &&
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CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},
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{v8s16, p0, 128, false},
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{v4s32, p0, 128, false},
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{v2s64, p0, 128, false}}))
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if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign(
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Query, {{v16s8, p0, 128, NoAlignRequirements},
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{v8s16, p0, 128, NoAlignRequirements},
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{v4s32, p0, 128, NoAlignRequirements},
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{v2s64, p0, 128, NoAlignRequirements}}))
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return true;
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return false;
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})
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@ -150,6 +150,19 @@ static bool isFloatingPointOpcodeDef(unsigned Opc) {
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}
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}
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static bool isGprbTwoInstrUnalignedLoadOrStore(const MachineInstr *MI) {
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if (MI->getOpcode() == TargetOpcode::G_LOAD ||
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MI->getOpcode() == TargetOpcode::G_STORE) {
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auto MMO = *MI->memoperands_begin();
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MI->getMF()->getSubtarget());
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if (MMO->getSize() == 4 && (!STI.systemSupportsUnalignedAccess() &&
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MMO->getSize() > MMO->getAlignment()))
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return true;
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}
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return false;
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}
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static bool isAmbiguous(unsigned Opc) {
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switch (Opc) {
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case TargetOpcode::G_LOAD:
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@ -261,6 +274,11 @@ bool MipsRegisterBankInfo::TypeInfoForMF::visit(
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startVisit(MI);
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AmbiguousRegDefUseContainer DefUseContainer(MI);
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if (isGprbTwoInstrUnalignedLoadOrStore(MI)) {
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setTypes(MI, Integer);
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return true;
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}
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if (AmbiguousTy == InstType::Ambiguous &&
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(MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||
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MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))
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@ -0,0 +1,89 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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@float_align1 = common global float 0.000000e+00, align 1
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@float_align4 = common global float 0.000000e+00, align 4
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@i32_align8 = common global i32 0, align 8
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define float @load_float_align1() {
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entry:
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%0 = load float, float* @float_align1, align 1
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ret float %0
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}
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define float @load_float_align4() {
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entry:
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%0 = load float, float* @float_align4, align 4
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ret float %0
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}
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define i32 @load_i32_align8() {
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entry:
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%0 = load i32, i32* @i32_align8, align 8
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ret i32 %0
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}
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...
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---
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name: load_float_align1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_float_align1
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
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; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load 4 from @float_align1, align 1)
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; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load 4 from @float_align1, align 1)
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; MIPS32: $f0 = COPY [[LWR]]
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; MIPS32: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
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%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_float_align4
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_float_align4
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
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; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align4)
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; MIPS32: $f0 = COPY [[LWC1_]]
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; MIPS32: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align4
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%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_i32_align8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_i32_align8
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
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; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load 4 from @i32_align8, align 8)
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; MIPS32: $v0 = COPY [[LW]]
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; MIPS32: RetRA implicit $v0
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%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
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%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,90 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
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--- |
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@float_align1 = common global float 0.000000e+00, align 1
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@float_align8 = common global float 0.000000e+00, align 8
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@i32_align2 = common global i32 0, align 2
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define float @load_float_align1() {
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entry:
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%0 = load float, float* @float_align1, align 1
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ret float %0
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}
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define float @load_float_align8() {
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entry:
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%0 = load float, float* @float_align8, align 8
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ret float %0
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}
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define i32 @load_i32_align2() {
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entry:
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%0 = load i32, i32* @i32_align2, align 2
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ret i32 %0
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}
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...
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---
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name: load_float_align1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32R6-LABEL: name: load_float_align1
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; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
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; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
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; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align1, align 1)
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; MIPS32R6: $f0 = COPY [[LWC1_]]
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; MIPS32R6: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
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%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_float_align8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32R6-LABEL: name: load_float_align8
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; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
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; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
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; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align8, align 8)
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; MIPS32R6: $f0 = COPY [[LWC1_]]
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; MIPS32R6: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align8
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%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align8, align 8)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_i32_align2
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32R6-LABEL: name: load_i32_align2
|
||||
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
|
||||
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
|
||||
; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load 4 from @i32_align2, align 2)
|
||||
; MIPS32R6: $v0 = COPY [[LW]]
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align2, align 2)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
@ -0,0 +1,99 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define void @store_float_align1(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align4(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align8(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align1
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
|
||||
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
|
||||
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
|
||||
; MIPS32: SWL [[COPY1]], [[ADDiu]], 3 :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32: SWR [[COPY1]], [[ADDiu]], 0 :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32: RetRA
|
||||
%0:fprb(s32) = COPY $f12
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
%2:gprb(s32) = COPY %0(s32)
|
||||
G_STORE %2(s32), %1(p0) :: (store 4 into @float_align1, align 1)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align4
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align4
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
|
||||
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
|
||||
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
|
||||
; MIPS32: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align4)
|
||||
; MIPS32: RetRA
|
||||
%0:fprb(s32) = COPY $f12
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @float_align4
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align8
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
||||
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
|
||||
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
|
||||
; MIPS32: SW [[COPY]], [[ADDiu]], 0 :: (store 4 into @i32_align8, align 8)
|
||||
; MIPS32: RetRA
|
||||
%0:gprb(s32) = COPY $a0
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
|
||||
RetRA
|
||||
|
||||
...
|
||||
@ -0,0 +1,96 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align8 = common global float 0.000000e+00, align 8
|
||||
@i32_align2 = common global i32 0, align 2
|
||||
|
||||
define void @store_float_align1(float %a) #0 {
|
||||
entry:
|
||||
store float %a, float* @float_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align8(float %a) #0 {
|
||||
entry:
|
||||
store float %a, float* @float_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align2(i32 signext %a) #0 {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32R6-LABEL: name: store_float_align1
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
|
||||
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
|
||||
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
|
||||
; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32R6: RetRA
|
||||
%0:fprb(s32) = COPY $f12
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32R6-LABEL: name: store_float_align8
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
|
||||
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
|
||||
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
|
||||
; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align8, align 8)
|
||||
; MIPS32R6: RetRA
|
||||
%0:fprb(s32) = COPY $f12
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @float_align8
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align8, align 8)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align2
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32R6-LABEL: name: store_i32_align2
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
||||
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
|
||||
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
|
||||
; MIPS32R6: SW [[COPY]], [[ADDiu]], 0 :: (store 4 into @i32_align2, align 2)
|
||||
; MIPS32R6: RetRA
|
||||
%0:gprb(s32) = COPY $a0
|
||||
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align2, align 2)
|
||||
RetRA
|
||||
|
||||
...
|
||||
239
test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
Normal file
239
test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
Normal file
@ -0,0 +1,239 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align2 = common global float 0.000000e+00, align 2
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@float_align8 = common global float 0.000000e+00, align 8
|
||||
@i32_align1 = common global i32 0, align 1
|
||||
@i32_align2 = common global i32 0, align 2
|
||||
@i32_align4 = common global i32 0, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define float @load_float_align1() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align1, align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align2() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align2, align 2
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align4() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align4, align 4
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align8() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align8, align 8
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align1() {
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align1, align 1
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align2() {
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align2, align 2
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align4() {
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align4, align 4
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align8() {
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align8, align 8
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align1
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align1
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align1
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align2
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align2
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align2, align 2)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align2
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align2, align 2)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align2, align 2)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align4
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align4
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align4
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align8
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align8
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align8, align 8)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align8
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align8, align 8)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align8, align 8)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_i32_align1
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_i32_align1
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align1, align 1)
|
||||
; MIPS32: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
; MIPS32R6-LABEL: name: load_i32_align1
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align1, align 1)
|
||||
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align1, align 1)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_i32_align2
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_i32_align2
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align2, align 2)
|
||||
; MIPS32: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
; MIPS32R6-LABEL: name: load_i32_align2
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align2, align 2)
|
||||
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align2, align 2)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_i32_align4
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_i32_align4
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align4)
|
||||
; MIPS32: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
; MIPS32R6-LABEL: name: load_i32_align4
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align4)
|
||||
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align4)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_i32_align8
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_i32_align8
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
; MIPS32: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
; MIPS32R6-LABEL: name: load_i32_align8
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
271
test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
Normal file
271
test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
Normal file
@ -0,0 +1,271 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align2 = common global float 0.000000e+00, align 2
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@float_align8 = common global float 0.000000e+00, align 8
|
||||
@i32_align1 = common global i32 0, align 1
|
||||
@i32_align2 = common global i32 0, align 2
|
||||
@i32_align4 = common global i32 0, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define void @store_float_align1(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align2(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align4(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align8(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align1(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align2(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align4(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align8(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align1
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align1
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align1
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align2
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align2
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align2, align 2)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align2
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align2, align 2)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align2
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align2, align 2)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align4
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align4
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align4
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align8
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align8
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align8, align 8)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align8
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align8, align 8)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align8
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align8, align 8)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align1
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align1
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align1, align 1)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_i32_align1
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align1, align 1)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align1, align 1)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align2
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align2
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align2, align 2)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_i32_align2
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align2, align 2)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align2, align 2)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align4
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align4
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align4)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_i32_align4
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align4)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align4)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align8
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align8
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_i32_align8
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
|
||||
RetRA
|
||||
|
||||
...
|
||||
182
test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
Normal file
182
test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
Normal file
@ -0,0 +1,182 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r6 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R6
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align2 = common global float 0.000000e+00, align 2
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@float_align8 = common global float 0.000000e+00, align 8
|
||||
@i32_align1 = common global i32 0, align 1
|
||||
@i32_align2 = common global i32 0, align 2
|
||||
@i32_align4 = common global i32 0, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define float @load_float_align1() {
|
||||
; MIPS32-LABEL: load_float_align1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align1)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
|
||||
; MIPS32-NEXT: # implicit-def: $v0
|
||||
; MIPS32-NEXT: lwl $2, 3($1)
|
||||
; MIPS32-NEXT: lwr $2, 0($1)
|
||||
; MIPS32-NEXT: mtc1 $2, $f0
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_float_align1:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align1)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align1)
|
||||
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load float, float* @float_align1, align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align2() {
|
||||
; MIPS32-LABEL: load_float_align2:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align2)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
|
||||
; MIPS32-NEXT: # implicit-def: $v0
|
||||
; MIPS32-NEXT: lwl $2, 3($1)
|
||||
; MIPS32-NEXT: lwr $2, 0($1)
|
||||
; MIPS32-NEXT: mtc1 $2, $f0
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_float_align2:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align2)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align2)
|
||||
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load float, float* @float_align2, align 2
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align4() {
|
||||
; MIPS32-LABEL: load_float_align4:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align4)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align4)
|
||||
; MIPS32-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_float_align4:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align4)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align4)
|
||||
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load float, float* @float_align4, align 4
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align8() {
|
||||
; MIPS32-LABEL: load_float_align8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align8)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align8)
|
||||
; MIPS32-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_float_align8:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align8)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align8)
|
||||
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load float, float* @float_align8, align 8
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align1() {
|
||||
; MIPS32-LABEL: load_i32_align1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align1)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align1)
|
||||
; MIPS32-NEXT: # implicit-def: $v0
|
||||
; MIPS32-NEXT: lwl $2, 3($1)
|
||||
; MIPS32-NEXT: lwr $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_i32_align1:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align1)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align1)
|
||||
; MIPS32R6-NEXT: lw $2, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align1, align 1
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align2() {
|
||||
; MIPS32-LABEL: load_i32_align2:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align2)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align2)
|
||||
; MIPS32-NEXT: # implicit-def: $v0
|
||||
; MIPS32-NEXT: lwl $2, 3($1)
|
||||
; MIPS32-NEXT: lwr $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_i32_align2:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align2)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align2)
|
||||
; MIPS32R6-NEXT: lw $2, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align2, align 2
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align4() {
|
||||
; MIPS32-LABEL: load_i32_align4:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align4)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align4)
|
||||
; MIPS32-NEXT: lw $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_i32_align4:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align4)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align4)
|
||||
; MIPS32R6-NEXT: lw $2, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align4, align 4
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align8() {
|
||||
; MIPS32-LABEL: load_i32_align8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align8)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align8)
|
||||
; MIPS32-NEXT: lw $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: load_i32_align8:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align8)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align8)
|
||||
; MIPS32R6-NEXT: lw $2, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align8, align 8
|
||||
ret i32 %0
|
||||
}
|
||||
@ -249,8 +249,8 @@ define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b,
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%0 = load i64, i64* %i64_ptr_a, align 4
|
||||
%1 = load i64, i64* %i64_ptr_b, align 4
|
||||
%0 = load i64, i64* %i64_ptr_a, align 8
|
||||
%1 = load i64, i64* %i64_ptr_b, align 8
|
||||
br i1 %cnd, label %cond.true, label %cond.false
|
||||
|
||||
cond.true:
|
||||
@ -261,7 +261,7 @@ cond.false:
|
||||
|
||||
cond.end:
|
||||
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
|
||||
store i64 %cond, i64* %i64_ptr_c, align 4
|
||||
store i64 %cond, i64* %i64_ptr_c, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
178
test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
Normal file
178
test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
Normal file
@ -0,0 +1,178 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r6 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R6
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align2 = common global float 0.000000e+00, align 2
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@float_align8 = common global float 0.000000e+00, align 8
|
||||
@i32_align1 = common global i32 0, align 1
|
||||
@i32_align2 = common global i32 0, align 2
|
||||
@i32_align4 = common global i32 0, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define void @store_float_align1(float %a) {
|
||||
; MIPS32-LABEL: store_float_align1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align1)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
|
||||
; MIPS32-NEXT: mfc1 $2, $f12
|
||||
; MIPS32-NEXT: swl $2, 3($1)
|
||||
; MIPS32-NEXT: swr $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_float_align1:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align1)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align1)
|
||||
; MIPS32R6-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store float %a, float* @float_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align2(float %a) {
|
||||
; MIPS32-LABEL: store_float_align2:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align2)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
|
||||
; MIPS32-NEXT: mfc1 $2, $f12
|
||||
; MIPS32-NEXT: swl $2, 3($1)
|
||||
; MIPS32-NEXT: swr $2, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_float_align2:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align2)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align2)
|
||||
; MIPS32R6-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store float %a, float* @float_align2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align4(float %a) {
|
||||
; MIPS32-LABEL: store_float_align4:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align4)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align4)
|
||||
; MIPS32-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_float_align4:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align4)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align4)
|
||||
; MIPS32R6-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store float %a, float* @float_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align8(float %a) {
|
||||
; MIPS32-LABEL: store_float_align8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(float_align8)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(float_align8)
|
||||
; MIPS32-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_float_align8:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(float_align8)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align8)
|
||||
; MIPS32R6-NEXT: swc1 $f12, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store float %a, float* @float_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align1(i32 signext %a) {
|
||||
; MIPS32-LABEL: store_i32_align1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align1)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align1)
|
||||
; MIPS32-NEXT: swl $4, 3($1)
|
||||
; MIPS32-NEXT: swr $4, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_i32_align1:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align1)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align1)
|
||||
; MIPS32R6-NEXT: sw $4, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align2(i32 signext %a) {
|
||||
; MIPS32-LABEL: store_i32_align2:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align2)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align2)
|
||||
; MIPS32-NEXT: swl $4, 3($1)
|
||||
; MIPS32-NEXT: swr $4, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_i32_align2:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align2)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align2)
|
||||
; MIPS32R6-NEXT: sw $4, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align4(i32 signext %a) {
|
||||
; MIPS32-LABEL: store_i32_align4:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align4)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align4)
|
||||
; MIPS32-NEXT: sw $4, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_i32_align4:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align4)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align4)
|
||||
; MIPS32R6-NEXT: sw $4, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align8(i32 signext %a) {
|
||||
; MIPS32-LABEL: store_i32_align8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lui $1, %hi(i32_align8)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align8)
|
||||
; MIPS32-NEXT: sw $4, 0($1)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R6-LABEL: store_i32_align8:
|
||||
; MIPS32R6: # %bb.0: # %entry
|
||||
; MIPS32R6-NEXT: lui $1, %hi(i32_align8)
|
||||
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align8)
|
||||
; MIPS32R6-NEXT: sw $4, 0($1)
|
||||
; MIPS32R6-NEXT: jrc $ra
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align8, align 8
|
||||
ret void
|
||||
}
|
||||
@ -0,0 +1,97 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define float @load_float_align1() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align1, align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define float @load_float_align4() {
|
||||
entry:
|
||||
%0 = load float, float* @float_align4, align 4
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define i32 @load_i32_align8() {
|
||||
entry:
|
||||
%0 = load i32, i32* @i32_align8, align 8
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align1
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align1
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_float_align4
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_float_align4
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
|
||||
; MIPS32: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $f0
|
||||
; MIPS32R6-LABEL: name: load_float_align4
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
|
||||
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $f0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
|
||||
$f0 = COPY %0(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: load_i32_align8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
; MIPS32-LABEL: name: load_i32_align8
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
; MIPS32: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
; MIPS32R6-LABEL: name: load_i32_align8
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32R6: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
|
||||
; MIPS32R6: RetRA implicit $v0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
|
||||
$v0 = COPY %0(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
@ -34,8 +34,8 @@
|
||||
|
||||
define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
|
||||
entry:
|
||||
%0 = load i64, i64* %i64_ptr_a, align 4
|
||||
%1 = load i64, i64* %i64_ptr_b, align 4
|
||||
%0 = load i64, i64* %i64_ptr_a, align 8
|
||||
%1 = load i64, i64* %i64_ptr_b, align 8
|
||||
br i1 %cnd, label %cond.true, label %cond.false
|
||||
|
||||
cond.true: ; preds = %entry
|
||||
@ -46,7 +46,7 @@
|
||||
|
||||
cond.end: ; preds = %cond.false, %cond.true
|
||||
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
|
||||
store i64 %cond, i64* %i64_ptr_c, align 4
|
||||
store i64 %cond, i64* %i64_ptr_c, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -230,8 +230,8 @@ body: |
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a, align 4)
|
||||
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b, align 4)
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a)
|
||||
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b)
|
||||
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
|
||||
@ -244,7 +244,7 @@ body: |
|
||||
; MIPS32: successors: %bb.3(0x80000000)
|
||||
; MIPS32: bb.3.cond.end:
|
||||
; MIPS32: [[PHI:%[0-9]+]]:fprb(s64) = G_PHI [[LOAD]](s64), %bb.1, [[LOAD1]](s64), %bb.2
|
||||
; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store 8 into %ir.i64_ptr_c, align 4)
|
||||
; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store 8 into %ir.i64_ptr_c)
|
||||
; MIPS32: RetRA
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
@ -253,8 +253,8 @@ body: |
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(p0) = COPY $a3
|
||||
%5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.i64_ptr_a, align 4)
|
||||
%6:_(s64) = G_LOAD %2(p0) :: (load 8 from %ir.i64_ptr_b, align 4)
|
||||
%5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.i64_ptr_a)
|
||||
%6:_(s64) = G_LOAD %2(p0) :: (load 8 from %ir.i64_ptr_b)
|
||||
%9:_(s32) = G_CONSTANT i32 1
|
||||
%10:_(s32) = COPY %4(s32)
|
||||
%8:_(s32) = G_AND %10, %9
|
||||
@ -268,7 +268,7 @@ body: |
|
||||
|
||||
bb.4.cond.end:
|
||||
%7:_(s64) = G_PHI %5(s64), %bb.2, %6(s64), %bb.3
|
||||
G_STORE %7(s64), %3(p0) :: (store 8 into %ir.i64_ptr_c, align 4)
|
||||
G_STORE %7(s64), %3(p0) :: (store 8 into %ir.i64_ptr_c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
|
||||
110
test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
Normal file
110
test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
Normal file
@ -0,0 +1,110 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
|
||||
--- |
|
||||
|
||||
@float_align1 = common global float 0.000000e+00, align 1
|
||||
@float_align4 = common global float 0.000000e+00, align 4
|
||||
@i32_align8 = common global i32 0, align 8
|
||||
|
||||
define void @store_float_align1(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align1, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float_align4(float %a) {
|
||||
entry:
|
||||
store float %a, float* @float_align4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_align8(i32 signext %a) {
|
||||
entry:
|
||||
store i32 %a, i32* @i32_align8, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align1
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: G_STORE [[COPY1]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align1
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align1
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_float_align4
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; MIPS32-LABEL: name: store_float_align4
|
||||
; MIPS32: liveins: $f12
|
||||
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_float_align4
|
||||
; MIPS32R6: liveins: $f12
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(p0) = G_GLOBAL_VALUE @float_align4
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: store_i32_align8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0
|
||||
|
||||
; MIPS32-LABEL: name: store_i32_align8
|
||||
; MIPS32: liveins: $a0
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
|
||||
; MIPS32: RetRA
|
||||
; MIPS32R6-LABEL: name: store_i32_align8
|
||||
; MIPS32R6: liveins: $a0
|
||||
; MIPS32R6: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
|
||||
; MIPS32R6: RetRA
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
|
||||
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
|
||||
RetRA
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user