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[ARM,MVE] Add intrinsics for scalar shifts.
This fills in the small family of MVE intrinsics that have nothing to do with vectors: they implement bit-shift operations on 32- or 64-bit values held in one or two general-purpose registers. Most of these shift operations saturate if shifting left, and round to nearest if shifting right, although LSLL and ASRL behave like ordinary shifts. When these instructions take a variable shift count in a register, they pay attention to its sign, so that (for example) LSLL or UQRSHLL will shift left if given a positive number but right if given a negative one. That makes even LSLL and ASRL different enough from standard LLVM IR shift semantics that I couldn't see any better alternative than to simply model the whole family as a set of MVE-specific IR intrinsics. (The //immediate// forms of LSLL and ASRL, on the other hand, do behave exactly like a standard IR shift of a 64-bit value. In fact, those forms don't have ACLE intrinsics defined at all, because you can just write an ordinary C shift operation if you want one of those.) The 64-bit shifts have to be instruction-selected in C++, because they deliver two output values. But the 32-bit ones are simple enough that I could write a DAG isel pattern directly into each Instruction record. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70319
This commit is contained in:
Simon Tatham
parent
3b2b582539
commit
7935cf1c34
@ -850,9 +850,25 @@ defm int_arm_mve_vstr_scatter_offset: MVEPredicated<
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[], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_anyvector_ty,
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llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrWriteMem]>;
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def int_arm_mve_urshrl: Intrinsic<
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[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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// MVE scalar shifts.
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class ARM_MVE_qrshift_single<list<LLVMType> value,
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list<LLVMType> saturate = []> :
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Intrinsic<value, value # [llvm_i32_ty] # saturate, [IntrNoMem]>;
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multiclass ARM_MVE_qrshift<list<LLVMType> saturate = []> {
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// Most of these shifts come in 32- and 64-bit versions. But only
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// the 64-bit ones have the extra saturation argument (if any).
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def "": ARM_MVE_qrshift_single<[llvm_i32_ty]>;
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def l: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty], saturate>;
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}
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defm int_arm_mve_urshr: ARM_MVE_qrshift;
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defm int_arm_mve_uqshl: ARM_MVE_qrshift;
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defm int_arm_mve_srshr: ARM_MVE_qrshift;
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defm int_arm_mve_sqshl: ARM_MVE_qrshift;
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defm int_arm_mve_uqrshl: ARM_MVE_qrshift<[llvm_i32_ty]>;
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defm int_arm_mve_sqrshr: ARM_MVE_qrshift<[llvm_i32_ty]>;
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// LSLL and ASRL only have 64-bit versions, not 32.
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def int_arm_mve_lsll: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
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def int_arm_mve_asrl: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
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def int_arm_mve_vadc: Intrinsic<
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[llvm_anyvector_ty, llvm_i32_ty],
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@ -226,7 +226,8 @@ private:
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void SelectMVE_WB(SDNode *N, const uint16_t *Opcodes, bool Predicated);
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/// SelectMVE_LongShift - Select MVE 64-bit scalar shift intrinsics.
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void SelectMVE_LongShift(SDNode *N, uint16_t Opcode, bool Immediate);
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void SelectMVE_LongShift(SDNode *N, uint16_t Opcode, bool Immediate,
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bool HasSaturationOperand);
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/// SelectMVE_VADCSBC - Select MVE vector add/sub-with-carry intrinsics.
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void SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry,
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@ -2399,7 +2400,8 @@ void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes,
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}
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void ARMDAGToDAGISel::SelectMVE_LongShift(SDNode *N, uint16_t Opcode,
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bool Immediate) {
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bool Immediate,
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bool HasSaturationOperand) {
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SDLoc Loc(N);
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SmallVector<SDValue, 8> Ops;
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@ -2410,11 +2412,18 @@ void ARMDAGToDAGISel::SelectMVE_LongShift(SDNode *N, uint16_t Opcode,
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// The shift count
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if (Immediate) {
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int32_t ImmValue = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
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Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate offset
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Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count
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} else {
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Ops.push_back(N->getOperand(3));
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}
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// The immediate saturation operand, if any
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if (HasSaturationOperand) {
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int32_t SatOp = cast<ConstantSDNode>(N->getOperand(4))->getZExtValue();
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int SatBit = (SatOp == 64 ? 0 : 1);
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Ops.push_back(getI32Imm(SatBit, Loc));
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}
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// MVE scalar shifts are IT-predicable, so include the standard
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// predicate arguments.
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Ops.push_back(getAL(CurDAG, Loc));
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@ -4267,7 +4276,28 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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break;
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case Intrinsic::arm_mve_urshrl:
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SelectMVE_LongShift(N, ARM::MVE_URSHRL, true);
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SelectMVE_LongShift(N, ARM::MVE_URSHRL, true, false);
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return;
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case Intrinsic::arm_mve_uqshll:
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SelectMVE_LongShift(N, ARM::MVE_UQSHLL, true, false);
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return;
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case Intrinsic::arm_mve_srshrl:
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SelectMVE_LongShift(N, ARM::MVE_SRSHRL, true, false);
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return;
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case Intrinsic::arm_mve_sqshll:
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SelectMVE_LongShift(N, ARM::MVE_SQSHLL, true, false);
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return;
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case Intrinsic::arm_mve_uqrshll:
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SelectMVE_LongShift(N, ARM::MVE_UQRSHLL, false, true);
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return;
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case Intrinsic::arm_mve_sqrshrl:
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SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true);
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return;
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case Intrinsic::arm_mve_lsll:
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SelectMVE_LongShift(N, ARM::MVE_LSLLr, false, false);
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return;
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case Intrinsic::arm_mve_asrl:
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SelectMVE_LongShift(N, ARM::MVE_ASRLr, false, false);
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return;
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case Intrinsic::arm_mve_vadc:
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@ -409,9 +409,12 @@ class MVE_ScalarShiftSingleReg<string iname, dag iops, string asm, string cstr,
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let Inst{19-16} = RdaDest{3-0};
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}
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class MVE_ScalarShiftSRegImm<string iname, bits<2> op5_4, list<dag> pattern=[]>
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class MVE_ScalarShiftSRegImm<string iname, bits<2> op5_4>
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: MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, long_shift:$imm),
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"$RdaSrc, $imm", "$RdaDest = $RdaSrc", pattern> {
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"$RdaSrc, $imm", "$RdaDest = $RdaSrc",
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[(set rGPR:$RdaDest,
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(i32 (!cast<Intrinsic>("int_arm_mve_" # iname)
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(i32 rGPR:$RdaSrc), (i32 imm:$imm))))]> {
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bits<5> imm;
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let Inst{15} = 0b0;
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@ -427,9 +430,12 @@ def MVE_SRSHR : MVE_ScalarShiftSRegImm<"srshr", 0b10>;
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def MVE_UQSHL : MVE_ScalarShiftSRegImm<"uqshl", 0b00>;
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def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;
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class MVE_ScalarShiftSRegReg<string iname, bits<2> op5_4, list<dag> pattern=[]>
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class MVE_ScalarShiftSRegReg<string iname, bits<2> op5_4>
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: MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
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"$RdaSrc, $Rm", "$RdaDest = $RdaSrc", pattern> {
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"$RdaSrc, $Rm", "$RdaDest = $RdaSrc",
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[(set rGPR:$RdaDest,
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(i32 (!cast<Intrinsic>("int_arm_mve_" # iname)
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(i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> {
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bits<4> Rm;
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let Inst{15-12} = Rm{3-0};
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@ -1,7 +1,264 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc i64 @test_urshrl(i64 %value) {
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define i64 @test_asrl(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_asrl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %2, i32 %1, i32 %shift)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32)
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define i64 @test_lsll(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_lsll:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 %shift)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32)
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define i32 @test_sqrshr(i32 %value, i32 %shift) {
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; CHECK-LABEL: test_sqrshr:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sqrshr r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.sqrshr(i32 %value, i32 %shift)
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ret i32 %0
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}
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declare i32 @llvm.arm.mve.sqrshr(i32, i32)
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define i64 @test_sqrshrl(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_sqrshrl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sqrshrl r0, r1, #64, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %2, i32 %1, i32 %shift, i32 64)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32)
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define i64 @test_sqrshrl_sat48(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_sqrshrl_sat48:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sqrshrl r0, r1, #48, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %2, i32 %1, i32 %shift, i32 48)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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define i32 @test_sqshl(i32 %value) {
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; CHECK-LABEL: test_sqshl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sqshl r0, #2
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.sqshl(i32 %value, i32 2)
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ret i32 %0
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}
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declare i32 @llvm.arm.mve.sqshl(i32, i32)
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define i64 @test_sqshll(i64 %value) {
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; CHECK-LABEL: test_sqshll:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sqshll r0, r1, #17
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %2, i32 %1, i32 17)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32)
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define i32 @test_srshr(i32 %value) {
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; CHECK-LABEL: test_srshr:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: srshr r0, #6
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.srshr(i32 %value, i32 6)
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ret i32 %0
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}
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declare i32 @llvm.arm.mve.srshr(i32, i32)
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define i64 @test_srshrl(i64 %value) {
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; CHECK-LABEL: test_srshrl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: srshrl r0, r1, #26
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %2, i32 %1, i32 26)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32)
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define i32 @test_uqrshl(i32 %value, i32 %shift) {
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; CHECK-LABEL: test_uqrshl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: uqrshl r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.uqrshl(i32 %value, i32 %shift)
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ret i32 %0
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}
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declare i32 @llvm.arm.mve.uqrshl(i32, i32)
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define i64 @test_uqrshll(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_uqrshll:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: uqrshll r0, r1, #64, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %2, i32 %1, i32 %shift, i32 64)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32)
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define i64 @test_uqrshll_sat48(i64 %value, i32 %shift) {
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; CHECK-LABEL: test_uqrshll_sat48:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: uqrshll r0, r1, #48, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %value, 32
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%1 = trunc i64 %0 to i32
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%2 = trunc i64 %value to i32
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%3 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %2, i32 %1, i32 %shift, i32 48)
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%4 = extractvalue { i32, i32 } %3, 1
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = extractvalue { i32, i32 } %3, 0
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%8 = zext i32 %7 to i64
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%9 = or i64 %6, %8
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ret i64 %9
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}
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|
||||
define i32 @test_uqshl(i32 %value) {
|
||||
; CHECK-LABEL: test_uqshl:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: uqshl r0, #21
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.arm.mve.uqshl(i32 %value, i32 21)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.arm.mve.uqshl(i32, i32)
|
||||
|
||||
define i64 @test_uqshll(i64 %value) {
|
||||
; CHECK-LABEL: test_uqshll:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: uqshll r0, r1, #16
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = lshr i64 %value, 32
|
||||
%1 = trunc i64 %0 to i32
|
||||
%2 = trunc i64 %value to i32
|
||||
%3 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %2, i32 %1, i32 16)
|
||||
%4 = extractvalue { i32, i32 } %3, 1
|
||||
%5 = zext i32 %4 to i64
|
||||
%6 = shl i64 %5, 32
|
||||
%7 = extractvalue { i32, i32 } %3, 0
|
||||
%8 = zext i32 %7 to i64
|
||||
%9 = or i64 %6, %8
|
||||
ret i64 %9
|
||||
}
|
||||
|
||||
declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32)
|
||||
|
||||
define i32 @test_urshr(i32 %value) {
|
||||
; CHECK-LABEL: test_urshr:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: urshr r0, #22
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.arm.mve.urshr(i32 %value, i32 22)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.arm.mve.urshr(i32, i32)
|
||||
|
||||
define i64 @test_urshrl(i64 %value) {
|
||||
; CHECK-LABEL: test_urshrl:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: urshrl r0, r1, #6
|
||||
@ -10,10 +267,10 @@ entry:
|
||||
%0 = lshr i64 %value, 32
|
||||
%1 = trunc i64 %0 to i32
|
||||
%2 = trunc i64 %value to i32
|
||||
%3 = tail call { i32, i32 } @llvm.arm.mve.urshrl(i32 %2, i32 %1, i32 6)
|
||||
%3 = call { i32, i32 } @llvm.arm.mve.urshrl(i32 %2, i32 %1, i32 6)
|
||||
%4 = extractvalue { i32, i32 } %3, 1
|
||||
%5 = zext i32 %4 to i64
|
||||
%6 = shl nuw i64 %5, 32
|
||||
%6 = shl i64 %5, 32
|
||||
%7 = extractvalue { i32, i32 } %3, 0
|
||||
%8 = zext i32 %7 to i64
|
||||
%9 = or i64 %6, %8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user