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[AMDGPU] calling conventions for AMDPAL OS type

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Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502
This commit is contained in:
Tim Renouf 2017-09-29 09:51:22 +00:00
parent 9e2adaa646
commit 7937cd8c35
20 changed files with 197 additions and 9 deletions
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23
include/llvm/IR/CallingConv.h
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@ -183,16 +183,18 @@ namespace CallingConv {
/// which have an "optimized" convention to preserve registers.
AVR_BUILTIN = 86,
/// Calling convention used for Mesa vertex shaders.
/// Calling convention used for Mesa vertex shaders, or AMDPAL last shader
/// stage before rasterization (vertex shader if tessellation and geometry
/// are not in use, or otherwise copy shader if one is needed).
AMDGPU_VS = 87,
/// Calling convention used for Mesa geometry shaders.
/// Calling convention used for Mesa/AMDPAL geometry shaders.
AMDGPU_GS = 88,
/// Calling convention used for Mesa pixel shaders.
/// Calling convention used for Mesa/AMDPAL pixel shaders.
AMDGPU_PS = 89,
/// Calling convention used for Mesa compute shaders.
/// Calling convention used for Mesa/AMDPAL compute shaders.
AMDGPU_CS = 90,
/// Calling convention for AMDGPU code object kernels.
@ -201,14 +203,23 @@ namespace CallingConv {
/// Register calling convention used for parameters transfer optimization
X86_RegCall = 92,
/// Calling convention used for Mesa hull shaders. (= tessellation control
/// shaders)
/// Calling convention used for Mesa/AMDPAL hull shaders (= tessellation
/// control shaders).
AMDGPU_HS = 93,
/// Calling convention used for special MSP430 rtlib functions
/// which have an "optimized" convention using additional registers.
MSP430_BUILTIN = 94,
/// Calling convention used for AMDPAL vertex shader if tessellation is in
/// use.
AMDGPU_LS = 95,
/// Calling convention used for AMDPAL shader stage before geometry shader
/// if geometry is in use. So either the domain (= tessellation evaluation)
/// shader if tessellation is in use, or otherwise the vertex shader.
AMDGPU_ES = 96,
/// The highest possible calling convention ID. Must be some 2^k - 1.
MaxID = 1023
};

2
lib/AsmParser/LLLexer.cpp
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@ -601,7 +601,9 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(hhvm_ccc);
KEYWORD(cxx_fast_tlscc);
KEYWORD(amdgpu_vs);
KEYWORD(amdgpu_ls);
KEYWORD(amdgpu_hs);
KEYWORD(amdgpu_es);
KEYWORD(amdgpu_gs);
KEYWORD(amdgpu_ps);
KEYWORD(amdgpu_cs);

4
lib/AsmParser/LLParser.cpp
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@ -1692,7 +1692,9 @@ void LLParser::ParseOptionalDLLStorageClass(unsigned &Res) {
/// ::= 'hhvm_ccc'
/// ::= 'cxx_fast_tlscc'
/// ::= 'amdgpu_vs'
/// ::= 'amdgpu_ls'
/// ::= 'amdgpu_hs'
/// ::= 'amdgpu_es'
/// ::= 'amdgpu_gs'
/// ::= 'amdgpu_ps'
/// ::= 'amdgpu_cs'
@ -1734,7 +1736,9 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
case lltok::kw_hhvm_ccc: CC = CallingConv::HHVM_C; break;
case lltok::kw_cxx_fast_tlscc: CC = CallingConv::CXX_FAST_TLS; break;
case lltok::kw_amdgpu_vs: CC = CallingConv::AMDGPU_VS; break;
case lltok::kw_amdgpu_ls: CC = CallingConv::AMDGPU_LS; break;
case lltok::kw_amdgpu_hs: CC = CallingConv::AMDGPU_HS; break;
case lltok::kw_amdgpu_es: CC = CallingConv::AMDGPU_ES; break;
case lltok::kw_amdgpu_gs: CC = CallingConv::AMDGPU_GS; break;
case lltok::kw_amdgpu_ps: CC = CallingConv::AMDGPU_PS; break;
case lltok::kw_amdgpu_cs: CC = CallingConv::AMDGPU_CS; break;

2
lib/AsmParser/LLToken.h
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@ -153,7 +153,9 @@ enum Kind {
kw_hhvm_ccc,
kw_cxx_fast_tlscc,
kw_amdgpu_vs,
kw_amdgpu_ls,
kw_amdgpu_hs,
kw_amdgpu_es,
kw_amdgpu_gs,
kw_amdgpu_ps,
kw_amdgpu_cs,

2
lib/IR/AsmWriter.cpp
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@ -373,7 +373,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
case CallingConv::HHVM: Out << "hhvmcc"; break;
case CallingConv::HHVM_C: Out << "hhvm_ccc"; break;
case CallingConv::AMDGPU_VS: Out << "amdgpu_vs"; break;
case CallingConv::AMDGPU_LS: Out << "amdgpu_ls"; break;
case CallingConv::AMDGPU_HS: Out << "amdgpu_hs"; break;
case CallingConv::AMDGPU_ES: Out << "amdgpu_es"; break;
case CallingConv::AMDGPU_GS: Out << "amdgpu_gs"; break;
case CallingConv::AMDGPU_PS: Out << "amdgpu_ps"; break;
case CallingConv::AMDGPU_CS: Out << "amdgpu_cs"; break;

5
lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
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@ -129,8 +129,11 @@ bool AMDGPUAAResult::pointsToConstantMemory(const MemoryLocation &Loc,
switch (F->getCallingConv()) {
default:
return AAResultBase::pointsToConstantMemory(Loc, OrLocal);
case CallingConv::AMDGPU_VS:
case CallingConv::AMDGPU_LS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_GS:
case CallingConv::AMDGPU_VS:
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_KERNEL:

4
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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@ -865,10 +865,12 @@ static unsigned getRsrcReg(CallingConv::ID CallConv) {
switch (CallConv) {
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
}
}

4
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -848,6 +848,8 @@ CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_LS:
return CC_AMDGPU;
case CallingConv::C:
case CallingConv::Fast:
@ -869,6 +871,8 @@ CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_LS:
return RetCC_SI_Shader;
case CallingConv::C:
case CallingConv::Fast:

2
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
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@ -491,7 +491,9 @@ static bool isArgPassedInSGPR(const Argument *A) {
case CallingConv::SPIR_KERNEL:
return true;
case CallingConv::AMDGPU_VS:
case CallingConv::AMDGPU_LS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_GS:
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:

2
lib/Target/AMDGPU/SIDefines.h
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@ -375,7 +375,9 @@ enum SDWA9EncValues{
#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)

6
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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@ -486,7 +486,9 @@ unsigned getInitialPSInputAddr(const Function &F) {
bool isShader(CallingConv::ID cc) {
switch(cc) {
case CallingConv::AMDGPU_VS:
case CallingConv::AMDGPU_LS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_GS:
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
@ -508,7 +510,9 @@ bool isEntryFunctionCC(CallingConv::ID CC) {
case CallingConv::AMDGPU_GS:
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_LS:
return true;
default:
return false;
@ -744,7 +748,9 @@ bool isArgPassedInSGPR(const Argument *A) {
case CallingConv::SPIR_KERNEL:
return true;
case CallingConv::AMDGPU_VS:
case CallingConv::AMDGPU_LS:
case CallingConv::AMDGPU_HS:
case CallingConv::AMDGPU_ES:
case CallingConv::AMDGPU_GS:
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:

8
test/Bitcode/compatibility.ll
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@ -476,6 +476,14 @@ declare cc93 void @f.cc93()
; CHECK: declare amdgpu_hs void @f.cc93()
declare amdgpu_hs void @f.amdgpu_hs()
; CHECK: declare amdgpu_hs void @f.amdgpu_hs()
declare cc95 void @f.cc95()
; CHECK: declare amdgpu_ls void @f.cc95()
declare amdgpu_ls void @f.amdgpu_ls()
; CHECK: declare amdgpu_ls void @f.amdgpu_ls()
declare cc96 void @f.cc96()
; CHECK: declare amdgpu_es void @f.cc96()
declare amdgpu_es void @f.amdgpu_es()
; CHECK: declare amdgpu_es void @f.amdgpu_es()
declare cc1023 void @f.cc1023()
; CHECK: declare cc1023 void @f.cc1023()

13
test/CodeGen/AMDGPU/amdpal-cs.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 47176
; GCN-LABEL: {{^}}cs_amdpal:
define amdgpu_cs half @cs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

13
test/CodeGen/AMDGPU/amdpal-es.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; amdpal pixel shader: check for 45864 (SPI_SHADER_PGM_RSRC1_ES) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45864
; GCN-LABEL: {{^}}es_amdpal:
define amdgpu_es half @es_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

14
test/CodeGen/AMDGPU/amdpal-gs.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal pixel shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45608
; GCN-LABEL: {{^}}gs_amdpal:
define amdgpu_gs half @gs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

14
test/CodeGen/AMDGPU/amdpal-hs.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal pixel shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 46120
; GCN-LABEL: {{^}}hs_amdpal:
define amdgpu_hs half @hs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

13
test/CodeGen/AMDGPU/amdpal-ls.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; amdpal pixel shader: check for 46376 (SPI_SHADER_PGM_RSRC1_LS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 46376
; GCN-LABEL: {{^}}ls_amdpal:
define amdgpu_ls half @ls_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

14
test/CodeGen/AMDGPU/amdpal-ps.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45096
; GCN-LABEL: {{^}}ps_amdpal:
define amdgpu_ps half @ps_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

14
test/CodeGen/AMDGPU/amdpal-vs.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
; amdpal pixel shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45352
; GCN-LABEL: {{^}}vs_amdpal:
define amdgpu_vs half @vs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}

45
test/CodeGen/AMDGPU/calling-conventions.ll
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@ -76,4 +76,49 @@ define amdgpu_kernel void @call_fastcc() #0 {
ret void
}
; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 47176
; GCN-LABEL: {{^}}cs_mesa:
define amdgpu_cs half @cs_mesa(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45096
; GCN-LABEL: {{^}}ps_mesa:
define amdgpu_ps half @ps_mesa(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45352
; GCN-LABEL: {{^}}vs_mesa:
define amdgpu_vs half @vs_mesa(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 45608
; GCN-LABEL: {{^}}gs_mesa:
define amdgpu_gs half @gs_mesa(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
; GCN-LABEL: .AMDGPU.config
; GCN: .long 46120
; GCN-LABEL: {{^}}hs_mesa:
define amdgpu_hs half @hs_mesa(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
attributes #0 = { nounwind noinline }