diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp
index ff34ac405a3..9d7b936a950 100644
--- a/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/lib/Target/ARM/ARMFrameLowering.cpp
@@ -482,7 +482,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   if (DPRCSSize > 0) {
     // Since vpush register list cannot have gaps, there may be multiple vpush
     // instructions in the prologue.
-    while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
+    while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
       DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
       LastPush = MBBI++;
     }
diff --git a/test/CodeGen/ARM/pr32578.ll b/test/CodeGen/ARM/pr32578.ll
new file mode 100644
index 00000000000..541ba35e5be
--- /dev/null
+++ b/test/CodeGen/ARM/pr32578.ll
@@ -0,0 +1,27 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple = "armv7"
+
+; CHECK-LABEL: func:
+; CHECK: push {r11, lr}
+; CHECK: vpush {d8}
+; CEHCK: b .LBB0_2
+define arm_aapcscc double @func() {
+  br label %tailrecurse
+
+tailrecurse:
+  %v0 = load i16, i16* undef, align 8
+  %cond36.i = icmp eq i16 %v0, 3
+  br i1 %cond36.i, label %sw.bb.i, label %sw.epilog.i
+
+sw.bb.i:
+  %v1 = load double, double* undef, align 8
+  %call21.i = tail call arm_aapcscc double @func()
+  %mul.i = fmul double %v1, %call21.i
+  ret double %mul.i
+
+sw.epilog.i:
+  tail call arm_aapcscc void @_ZNK10shared_ptrdeEv()
+  br label %tailrecurse
+}
+
+declare arm_aapcscc void @_ZNK10shared_ptrdeEv() local_unnamed_addr