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[TableGen] Allow BitsInit to init integer in pseudo expansion

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Differential Revision: https://reviews.llvm.org/D99057
This commit is contained in:
Serge Pavlov 2021-03-20 13:06:46 +07:00
parent 325b500b46
commit 7a00ea0bf0
2 changed files with 43 additions and 0 deletions
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37
test/TableGen/pseudo-inst-expansion.td Normal file
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@ -0,0 +1,37 @@
// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo;
}
def REG : Register<"REG">;
def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
class SysReg<bits<12> op> {
bits<12> Encoding = op;
}
def SR : SysReg<0b111100001111>;
class Pseudo<dag outs, dag ins, list<dag> pattern>
: Instruction {
dag OutOperandList = outs;
dag InOperandList = ins;
let Pattern = pattern;
let isPseudo = 1;
}
def INSTR : Instruction {
let OutOperandList = (outs GPR:$rd);
let InOperandList = (ins i32imm:$val);
let Pattern = [];
}
def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
[(set GPR:$rd, (i32 SR.Encoding))]>,
PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
// CHECK: .addOperand(MCOperand::createImm(3855));

6
utils/TableGen/PseudoLoweringEmitter.cpp
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@ -108,6 +108,12 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
OperandMap[BaseIdx + i].Kind = OpData::Imm;
OperandMap[BaseIdx + i].Data.Imm = II->getValue();
++OpsAdded;
} else if (auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
auto II = dyn_cast<IntInit>(BI->convertInitializerTo(IntRecTy::get()));
assert(II && "Cannot convert to integer initializer");
OperandMap[BaseIdx + i].Kind = OpData::Imm;
OperandMap[BaseIdx + i].Data.Imm = II->getValue();
++OpsAdded;
} else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
// Just add the operands recursively. This is almost certainly
// a constant value for a complex operand (> 1 MI operand).