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[X86] Move '0-x == y --> x+y == 0' and similar combines to EmitCmp.
AArch64 handles this pattern in their lowering code. By emitting CMN. ARM handles it as an isel pattern.
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@ -21209,6 +21209,24 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1);
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}
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// 0-x == y --> x+y == 0
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// 0-x != y --> x+y != 0
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if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op0.getOperand(0)) &&
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(X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
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SDVTList VTs = DAG.getVTList(CmpVT, MVT::i32);
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SDValue Add = DAG.getNode(X86ISD::ADD, dl, VTs, Op0.getOperand(1), Op1);
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return Add.getValue(1);
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}
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// x == 0-y --> x+y == 0
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// x != 0-y --> x+y != 0
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if (Op1.getOpcode() == ISD::SUB && isNullConstant(Op1.getOperand(0)) &&
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(X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
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SDVTList VTs = DAG.getVTList(CmpVT, MVT::i32);
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SDValue Add = DAG.getNode(X86ISD::ADD, dl, VTs, Op0, Op1.getOperand(1));
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return Add.getValue(1);
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}
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// Use SUB instead of CMP to enable CSE between SUB and CMP.
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SDVTList VTs = DAG.getVTList(CmpVT, MVT::i32);
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SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1);
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@ -44523,21 +44541,6 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
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SDLoc DL(N);
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if (CC == ISD::SETNE || CC == ISD::SETEQ) {
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// 0-x == y --> x+y == 0
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// 0-x != y --> x+y != 0
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if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
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LHS.hasOneUse()) {
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SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, RHS, LHS.getOperand(1));
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return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
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}
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// x == 0-y --> x+y == 0
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// x != 0-y --> x+y != 0
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if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
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RHS.hasOneUse()) {
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SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
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return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
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}
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if (SDValue V = combineVectorSizedSetCCEquality(N, DAG, Subtarget))
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return V;
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}
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