From 7a430ddf61da6ca1235afe3be21ed116dd4c19f0 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 19 Dec 2005 07:57:53 +0000
Subject: [PATCH] Fix pifft by correcting the case when a i64/f64 straddles O5
 and memory: we were storing into [FP+88] instead of [FP+92]. Improve codegen
 by emitting [FP+92], instead of emitting a copy of FP into another GPR which
 wouldn't be coallesced because FP isn't register allocated.

llvm-svn: 24859
---
 lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 195a32e7fb2..6c84d28311f 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -456,6 +456,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
       
       if (RegValuesToPass.size() >= 6) {
         ValToStore = Lo;
+        ArgOffset += 4;
+        ObjSize = 4;
       } else {
         RegValuesToPass.push_back(Lo);
       }
@@ -464,7 +466,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
     
     if (ValToStore.Val) {
       if (!StackPtr.Val) {
-        StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
+        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
         NullSV = DAG.getSrcValue(NULL);
       }
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@@ -893,6 +895,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
   
   switch (N->getOpcode()) {
   default: break;
+  case ISD::Register: return Op;
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     if (N->hasOneUse())