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[mips] Handle missing CondCodes

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Add patterns for unhandled CondCode enumerables:
SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE.

Stated at the ISD::CondCode enum declaration:
`All of these (except for the 'always folded ops')
should be handled for floating point.`

Add patterns which use these nodes, same as corresponding
'ordered' CondCode nodes.

Referring to 'Ordered means that neither operand is a QNAN'
we assume it is safe to match ex. SETLT node to the same
instruction as SETOLT.

Differential Revision: https://reviews.llvm.org/D50757

llvm-svn: 340392
This commit is contained in:
Stefan Maksimovic 2018-08-22 09:34:44 +00:00
parent f9e1fbc647
commit 7a65ab4d76
2 changed files with 92 additions and 0 deletions
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29
lib/Target/Mips/MipsMSAInstrInfo.td
View File

@ -107,6 +107,18 @@ class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
(ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
// ISD::SETFALSE cannot occur
def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
@ -4038,3 +4050,20 @@ def : MSAPat<
(SPLAT_D v2f64:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_64))>;
def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
(FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
(FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
(FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
(FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
(FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
(FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
(FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
(FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;

63
test/CodeGen/Mips/msa/cc_without_nan.ll Normal file
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@ -0,0 +1,63 @@
; RUN: llc -mtriple mips64-unknown-linux -mcpu=mips64r5 -mattr=+msa < %s | FileCheck %s
; The fcmp fast flag will result in conversion from
; setolt, setoeq, setole, setone to
; setlt, seteq, setle, setne nodes.
; Test that the latter nodes are matched to the same instructions as the former.
define <2 x i1> @testlt_v2f64(<2 x double> %a, <2 x double> %b) {
start:
%0 = fcmp fast olt <2 x double> %a, %b
; CHECK: fclt.d
ret <2 x i1> %0
}
define <4 x i1> @testlt_v4f32(<4 x float> %a, <4 x float> %b) {
start:
%0 = fcmp fast olt <4 x float> %a, %b
; CHECK: fclt.w
ret <4 x i1> %0
}
define <2 x i1> @testeq_v2f64(<2 x double> %a, <2 x double> %b) {
start:
%0 = fcmp fast oeq <2 x double> %a, %b
; CHECK: fceq.d
ret <2 x i1> %0
}
define <4 x i1> @testeq_v4f32(<4 x float> %a, <4 x float> %b) {
start:
%0 = fcmp fast oeq <4 x float> %a, %b
; CHECK: fceq.w
ret <4 x i1> %0
}
define <2 x i1> @testle_v2f64(<2 x double> %a, <2 x double> %b) {
start:
%0 = fcmp fast ole <2 x double> %a, %b
; CHECK: fcle.d
ret <2 x i1> %0
}
define <4 x i1> @testle_v4f32(<4 x float> %a, <4 x float> %b) {
start:
%0 = fcmp fast ole <4 x float> %a, %b
; CHECK: fcle.w
ret <4 x i1> %0
}
define <2 x i1> @testne_v2f64(<2 x double> %a, <2 x double> %b) {
start:
%0 = fcmp fast one <2 x double> %a, %b
; CHECK: fcne.d
ret <2 x i1> %0
}
define <4 x i1> @testne_v4f32(<4 x float> %a, <4 x float> %b) {
start:
%0 = fcmp fast one <4 x float> %a, %b
; CHECK: fcne.w
ret <4 x i1> %0
}