From 7a79f94aada0b2722130faf6a3cab41d88009326 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sat, 22 Oct 2011 12:39:25 +0000 Subject: [PATCH] Fix pr11193. SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724 --- lib/Target/X86/X86ISelLowering.cpp | 3 --- test/CodeGen/X86/2011-10-21-widen-cmp.ll | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 96f04e72981..7dec7c4e336 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -10146,9 +10146,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) DAG.getConstant(SHLIntrinsicsID, MVT::i32), Node->getOperand(0), ShAmt); - // In case of 1 bit sext, no need to shr - if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(SRAIntrinsicsID, MVT::i32), Tmp1, ShAmt); diff --git a/test/CodeGen/X86/2011-10-21-widen-cmp.ll b/test/CodeGen/X86/2011-10-21-widen-cmp.ll index aa1a60026f4..2fe645b0781 100644 --- a/test/CodeGen/X86/2011-10-21-widen-cmp.ll +++ b/test/CodeGen/X86/2011-10-21-widen-cmp.ll @@ -28,3 +28,18 @@ entry: store <2 x double> %1, <2 x double>* undef ret void } + +; CHECK: mp_11193 +; CHECK: psraw $15 +; CHECK: ret +define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) +nounwind { +allocas: + %bincmp = fcmp olt <8 x float> , + %t = extractelement <8 x i1> %bincmp, i32 0 + %ft = sitofp i1 %t to float + %pp = bitcast <8 x float>* %RET to float* + store float %ft, float* %pp + ret void +} +