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[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move

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The isTriviallyRematerializable hook is only called for instructions that are
tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely
be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of
the atomic-rmw.ll tests functions. It also avoids stack spills in two of our
out-of-tree CHERI tests.
ORI/XORI with zero may or may not be the same as a move micro-architecturally,
but since we are already doing it for register == x0, we might as well
do the same if the immediate is zero.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86480
This commit is contained in:
Alex Richardson 2020-08-25 15:44:57 +01:00
parent afd0abc1f8
commit 7a907ec504
6 changed files with 1600 additions and 2138 deletions
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16
lib/Target/RISCV/RISCVInstrInfo.cpp
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@ -512,13 +512,15 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
const unsigned Opcode = MI.getOpcode();
switch(Opcode) {
default:
break;
case RISCV::ADDI:
case RISCV::ORI:
case RISCV::XORI:
return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
switch (Opcode) {
default:
break;
case RISCV::ADDI:
case RISCV::ORI:
case RISCV::XORI:
return (MI.getOperand(1).isReg() &&
MI.getOperand(1).getReg() == RISCV::X0) ||
(MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
}
return MI.isAsCheapAsAMove();
}

3702
test/CodeGen/RISCV/atomic-rmw.ll
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File diff suppressed because it is too large Load Diff

4
test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
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@ -172,9 +172,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
@ -218,9 +218,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4

8
test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
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@ -368,7 +368,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi t0, zero, 8
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
@ -376,6 +375,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
@ -401,7 +401,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi t0, zero, 8
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
@ -409,6 +408,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
@ -693,9 +693,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
@ -736,9 +736,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4

2
test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
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@ -202,7 +202,6 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: addi t0, zero, 8
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3
@ -210,6 +209,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a6, zero, 7
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp)

6
test/CodeGen/RISCV/vararg.ll
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@ -1441,9 +1441,9 @@ define void @va5_aligned_stack_caller() nounwind {
; ILP32-ILP32F-FPELIM-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 688509
; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11
; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13
; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4
@ -1486,9 +1486,9 @@ define void @va5_aligned_stack_caller() nounwind {
; ILP32-ILP32F-WITHFP-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 688509
; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11
; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13
; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4
@ -1530,9 +1530,9 @@ define void @va5_aligned_stack_caller() nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a5, a0, 1311
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 688509
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4