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[llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.

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Now, flags will result in differing hashes for a given MI. In effect, if
you have two instructions with everything identical except for their
flags then you should get two different hashes and fewer collisions.

Differential Revision: https://reviews.llvm.org/D70479
This commit is contained in:
Puyan Lotfi 2019-12-10 04:40:36 -05:00
parent a6543a42ec
commit 7ac96363aa
2 changed files with 38 additions and 1 deletions
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2
lib/CodeGen/MIRVRegNamerUtils.cpp
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@ -69,7 +69,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
return 0;
};
SmallVector<unsigned, 16> MIOperands = {MI.getOpcode()};
SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());

37
test/CodeGen/MIR/X86/mircanon-flags.mir Normal file
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@ -0,0 +1,37 @@
# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -o - %s | FileCheck %s
# The purpose of this test is to ensure that differing flags do in-fact cause
# naming collisions with the new vreg renamers naming scheme.
--- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
define void @baz() { unreachable }
...
---
name: baz
body: |
bb.0:
; CHECK: COPY
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
%0:fr32 = COPY $xmm0
%1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
%2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
%3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
%4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
%5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
%6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
%7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
%8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
%9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
$xmm0 = COPY %9
RET 0, $xmm0
...