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RegisterCoalescer: Ignore interferences for constant physregs

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When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

llvm-svn: 286503
This commit is contained in:
Matthias Braun 2016-11-10 21:22:47 +00:00
parent a4fdadbaa3
commit 7ae7138a52
4 changed files with 59 additions and 26 deletions
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5
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -542,9 +542,8 @@ public:
void dumpUses(unsigned RegNo) const;
#endif
/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
/// throughout the function. It is safe to move instructions that read such
/// a physreg.
/// Returns true if PhysReg is unallocatable and constant throughout the
/// function. Writing to a constant register has no effect.
bool isConstantPhysReg(unsigned PhysReg) const;
/// Get an iterator over the pressure sets affected by the given physical or

46
lib/CodeGen/RegisterCoalescer.cpp
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@ -1570,11 +1570,13 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
// Deny any overlapping intervals. This depends on all the reserved
// register live ranges to look like dead defs.
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI)
if (RHS.overlaps(LIS->getRegUnit(*UI))) {
DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
return false;
}
if (!MRI->isConstantPhysReg(DstReg)) {
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI)
if (RHS.overlaps(LIS->getRegUnit(*UI))) {
DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
return false;
}
}
// Skip any value computations, we are not adding new values to the
// reserved register. Also skip merging the live ranges, the reserved
@ -1596,24 +1598,26 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
const SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
const SlotIndex DestRegIdx = LIS->getInstructionIndex(*DestMI).getRegSlot();
// We checked above that there are no interfering defs of the physical
// register. However, for this case, where we intent to move up the def of
// the physical register, we also need to check for interfering uses.
SlotIndexes *Indexes = LIS->getSlotIndexes();
for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
MachineInstr *MI = LIS->getInstructionFromIndex(SI);
if (MI->readsRegister(DstReg, TRI)) {
DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
return false;
}
// We must also check for clobbers caused by regmasks.
for (const auto &MO : MI->operands()) {
if (MO.isRegMask() && MO.clobbersPhysReg(DstReg)) {
DEBUG(dbgs() << "\t\tInterference (regmask clobber): " << *MI);
if (!MRI->isConstantPhysReg(DstReg)) {
// We checked above that there are no interfering defs of the physical
// register. However, for this case, where we intent to move up the def of
// the physical register, we also need to check for interfering uses.
SlotIndexes *Indexes = LIS->getSlotIndexes();
for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
MachineInstr *MI = LIS->getInstructionFromIndex(SI);
if (MI->readsRegister(DstReg, TRI)) {
DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
return false;
}
// We must also check for clobbers caused by regmasks.
for (const auto &MO : MI->operands()) {
if (MO.isRegMask() && MO.clobbersPhysReg(DstReg)) {
DEBUG(dbgs() << "\t\tInterference (regmask clobber): " << *MI);
return false;
}
}
}
}

3
test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
View File

@ -5,12 +5,11 @@
; The verifier would complain otherwise.
define i64 @csed-impdef-killflag(i64 %a) {
; CHECK-LABEL: csed-impdef-killflag
; CHECK-DAG: mov [[REG0:w[0-9]+]], wzr
; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
; CHECK: cmp x0, #0
; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], [[REG0]], [[REG1]], ne
; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]

31
test/CodeGen/AArch64/regcoal-constreg.mir Normal file
View File

@ -0,0 +1,31 @@
# RUN: llc -mtriple=aarch64-- -run-pass=simple-register-coalescing %s -o - | FileCheck %s
--- |
define void @func() { ret void }
...
---
# Check that we eliminate copies to/from constant physregs regardless of
# "interfering" reads/writes.
# CHECK: name: func
# CHECK-NOT: COPY
# CHECK: STRWui %wzr, %x1
# CHECK-NOT: COPY
# CHECK: STRXui %xzr, %x1
# CHECK: %wzr = SUBSWri %w1, 0, 0
name: func
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr64 }
- { id: 2, class: gpr32 }
body: |
bb.0:
%0 = COPY %wzr
dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
STRWui %0, %x1, 0
%1 = COPY %xzr
dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
STRXui %1, %x1, 0
%2 = SUBSWri %w1, 0, 0, implicit-def %nzcv
%wzr = COPY %2
...