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https://github.com/RPCS3/llvm-mirror.git
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Remove custom allocation orders in SystemZ.
Note that this actually changes code generation, and someone who understands this target better should check the changes. - R12Q is now allocatable. I think it was omitted from the allocation order by mistake since it isn't reserved. It as apparently used as a GOT pointer sometimes, and it should probably be reserved if that is the case. - The GR64 registers are allocated in a different order now. The register allocator will automatically put the CSRs last. There were other changes to the order that may have been significant. The test fix is because r0 and r1 swapped places in the allocation order. llvm-svn: 133067
This commit is contained in:
Jakob Stoklund Olesen
parent
30f84a59ae
commit
7b0de9a9e0
@ -51,10 +51,20 @@ BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF))
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11W);
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Reserved.set(SystemZ::R10P);
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Reserved.set(SystemZ::R10Q);
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}
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Reserved.set(SystemZ::R14D);
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R14W);
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Reserved.set(SystemZ::R15W);
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Reserved.set(SystemZ::R14P);
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Reserved.set(SystemZ::R14Q);
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return Reserved;
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}
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@ -168,45 +168,7 @@ def GR32 : RegisterClass<"SystemZ", [i32], 32,
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// Frame pointer, sometimes allocable
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R11W,
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// Volatile, but not allocable
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R14W, R15W]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG32[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W,
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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static const unsigned SystemZ_REG32_nofp[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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GR32Class::iterator
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GR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG32_nofp;
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else
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return SystemZ_REG32;
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}
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GR32Class::iterator
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GR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned));
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}
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}];
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}
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R14W, R15W]>;
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/// Registers used to generate address. Everything except R0.
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def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
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@ -215,45 +177,7 @@ def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
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// Frame pointer, sometimes allocable
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R11W,
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// Volatile, but not allocable
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R14W, R15W]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_ADDR32[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W,
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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static const unsigned SystemZ_ADDR32_nofp[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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ADDR32Class::iterator
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ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_ADDR32_nofp;
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else
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return SystemZ_ADDR32;
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}
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ADDR32Class::iterator
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ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
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else
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return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned));
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}
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}];
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}
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R14W, R15W]>;
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def GR64 : RegisterClass<"SystemZ", [i64], 64,
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// Volatile registers
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@ -261,45 +185,8 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64,
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// Frame pointer, sometimes allocable
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R11D,
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// Volatile, but not allocable
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R14D, R15D]>
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{
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R14D, R15D]> {
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let SubRegClasses = [(GR32 subreg_32bit)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG64[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D,
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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static const unsigned SystemZ_REG64_nofp[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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GR64Class::iterator
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GR64Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG64_nofp;
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else
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return SystemZ_REG64;
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}
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GR64Class::iterator
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GR64Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned));
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}
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}];
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}
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def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
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@ -308,168 +195,30 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
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// Frame pointer, sometimes allocable
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R11D,
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// Volatile, but not allocable
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R14D, R15D]>
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{
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R14D, R15D]> {
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let SubRegClasses = [(ADDR32 subreg_32bit)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_ADDR64[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D,
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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static const unsigned SystemZ_ADDR64_nofp[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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ADDR64Class::iterator
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ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_ADDR64_nofp;
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else
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return SystemZ_ADDR64;
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}
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ADDR64Class::iterator
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ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
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else
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return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned));
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}
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}];
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}
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// Even-odd register pairs
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def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
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[R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]>
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{
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[R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]> {
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let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG64P[] = {
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SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P,
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SystemZ::R8P, SystemZ::R6P };
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static const unsigned SystemZ_REG64P_nofp[] = {
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SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */
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SystemZ::R8P, SystemZ::R6P };
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GR64PClass::iterator
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GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG64P_nofp;
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else
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return SystemZ_REG64P;
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}
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GR64PClass::iterator
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GR64PClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned));
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}
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}];
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}
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def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
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[R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
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{
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[R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> {
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let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32),
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(GR64 subreg_even, subreg_odd)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG128[] = {
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SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q,
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SystemZ::R8Q, SystemZ::R6Q };
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static const unsigned SystemZ_REG128_nofp[] = {
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SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */
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SystemZ::R8Q, SystemZ::R6Q };
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GR128Class::iterator
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GR128Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG128_nofp;
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else
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return SystemZ_REG128;
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}
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GR128Class::iterator
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GR128Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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if (TFI->hasFP(MF))
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return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned));
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}
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}];
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}
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def FP32 : RegisterClass<"SystemZ", [f32], 32,
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[F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S,
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F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REGFP32[] = {
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SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S,
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SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S,
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SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
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FP32Class::iterator
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FP32Class::allocation_order_begin(const MachineFunction &MF) const {
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return SystemZ_REGFP32;
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}
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FP32Class::iterator
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FP32Class::allocation_order_end(const MachineFunction &MF) const {
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return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned));
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}
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}];
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}
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F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]>;
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def FP64 : RegisterClass<"SystemZ", [f64], 64,
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[F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L,
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[F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L,
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F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> {
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let SubRegClasses = [(FP32 subreg_32bit)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REGFP64[] = {
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SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L,
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SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L,
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SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
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SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L };
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FP64Class::iterator
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FP64Class::allocation_order_begin(const MachineFunction &MF) const {
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return SystemZ_REGFP64;
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}
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FP64Class::iterator
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FP64Class::allocation_order_end(const MachineFunction &MF) const {
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return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned));
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}
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}];
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}
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// Status flags registers.
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@ -12,7 +12,7 @@ define i16 @foo(i16 zeroext %a) zeroext {
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define i32 @foo2(i32 zeroext %a) zeroext {
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; CHECK: foo2:
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; CHECK: lrvr %r1, %r2
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; CHECK: lrvr [[R1:%r.]], %r2
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%res = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %res
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}
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@ -32,7 +32,7 @@ define i16 @foo4(i16* %b) zeroext {
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define i32 @foo5(i32* %b) zeroext {
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; CHECK: foo5:
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; CHECK: lrv %r1, 0(%r2)
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; CHECK: lrv [[R1:%r.]], 0(%r2)
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%a = load i32* %b
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%res = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %res
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