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[X86][SSE] Regenerate vector of pointers tests
llvm-svn: 289555
This commit is contained in:
Simon Pilgrim
parent
d429264556
commit
7b2c71035d
@ -1,135 +1,165 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 | FileCheck %s
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; RUN: opt -instsimplify -disable-output < %s
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;CHECK: SHUFF0
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define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind {
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; CHECK-LABEL: SHUFF0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,1,2]
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,1]
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retl
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entry:
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%G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <8 x i32> <i32 2, i32 7, i32 1, i32 2, i32 4, i32 5, i32 1, i32 1>
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;CHECK: pshufd
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ret <8 x i32*> %G
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;CHECK: ret
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}
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;CHECK: SHUFF1
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define <4 x i32*> @SHUFF1(<4 x i32*> %ptrv) nounwind {
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; CHECK-LABEL: SHUFF1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,3,2]
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; CHECK-NEXT: retl
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entry:
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%G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <4 x i32> <i32 2, i32 7, i32 7, i32 2>
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;CHECK: pshufd
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ret <4 x i32*> %G
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;CHECK: ret
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}
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;CHECK: SHUFF3
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define <4 x i8*> @SHUFF3(<4 x i8*> %ptrv) nounwind {
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; CHECK-LABEL: SHUFF3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,1,2]
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; CHECK-NEXT: retl
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entry:
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%G = shufflevector <4 x i8*> %ptrv, <4 x i8*> undef, <4 x i32> <i32 2, i32 7, i32 1, i32 2>
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;CHECK: pshufd
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD0
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define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind {
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; CHECK-LABEL: LOAD0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm0
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; CHECK-NEXT: retl
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entry:
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%G = load <4 x i8*>, <4 x i8*>* %p
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;CHECK: movaps
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD1
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define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind {
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; CHECK-LABEL: LOAD1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movdqa (%eax), %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,0,3]
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; CHECK-NEXT: movdqa %xmm1, (%eax)
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; CHECK-NEXT: retl
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entry:
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%G = load <4 x i8*>, <4 x i8*>* %p
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;CHECK: movdqa
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;CHECK: pshufd
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;CHECK: movdqa
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%T = shufflevector <4 x i8*> %G, <4 x i8*> %G, <4 x i32> <i32 7, i32 1, i32 4, i32 3>
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store <4 x i8*> %T, <4 x i8*>* %p
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD2
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define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind {
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; CHECK-LABEL: LOAD2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: subl $28, %esp
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm0
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; CHECK-NEXT: movaps %xmm0, (%esp)
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; CHECK-NEXT: addl $28, %esp
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; CHECK-NEXT: retl
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entry:
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%I = alloca <4 x i8*>
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;CHECK: sub
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%G = load <4 x i8*>, <4 x i8*>* %p
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;CHECK: movaps
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store <4 x i8*> %G, <4 x i8*>* %I
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;CHECK: movaps
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%Z = load <4 x i8*>, <4 x i8*>* %I
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ret <4 x i8*> %Z
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;CHECK: add
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;CHECK: ret
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}
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;CHECK: INT2PTR0
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define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind {
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; CHECK-LABEL: INT2PTR0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm0
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; CHECK-NEXT: retl
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entry:
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%G = load <4 x i8*>, <4 x i8*>* %p
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;CHECK: movl
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;CHECK: movaps
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%K = ptrtoint <4 x i8*> %G to <4 x i32>
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;CHECK: ret
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ret <4 x i32> %K
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}
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;CHECK: INT2PTR1
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define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
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; CHECK-LABEL: INT2PTR1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; CHECK-NEXT: retl
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entry:
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%G = load <4 x i8>, <4 x i8>* %p
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;CHECK: movl
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;CHECK: pmovzxbd (%
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%K = inttoptr <4 x i8> %G to <4 x i32*>
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;CHECK: ret
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ret <4 x i32*> %K
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}
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;CHECK: BITCAST0
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define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind {
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; CHECK-LABEL: BITCAST0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm0
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; CHECK-NEXT: retl
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entry:
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%G = load <4 x i8*>, <4 x i8*>* %p
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;CHECK: movl
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%T = bitcast <4 x i8*> %G to <4 x i32*>
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;CHECK: movaps
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;CHECK: ret
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ret <4 x i32*> %T
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}
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;CHECK: BITCAST1
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define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
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; CHECK-LABEL: BITCAST1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: retl
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entry:
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%G = load <2 x i8*>, <2 x i8*>* %p
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;CHECK: movl
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;CHECK: pmovzxdq
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%T = bitcast <2 x i8*> %G to <2 x i32*>
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;CHECK: ret
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ret <2 x i32*> %T
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}
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;CHECK: ICMP0
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define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
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; CHECK-LABEL: ICMP0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movdqa (%ecx), %xmm0
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; CHECK-NEXT: pcmpgtd (%eax), %xmm0
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
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; CHECK-NEXT: blendvps {{\.LCPI.*}}, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retl
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entry:
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%g0 = load <4 x i8*>, <4 x i8*>* %p0
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%g1 = load <4 x i8*>, <4 x i8*>* %p1
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%k = icmp sgt <4 x i8*> %g0, %g1
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;CHECK: pcmpgtd
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%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
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ret <4 x i32> %j
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;CHECK: ret
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}
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;CHECK: ICMP1
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define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
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; CHECK-LABEL: ICMP1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movdqa (%ecx), %xmm0
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; CHECK-NEXT: pcmpeqd (%eax), %xmm0
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
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; CHECK-NEXT: blendvps {{\.LCPI.*}}, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retl
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entry:
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%g0 = load <4 x i8*>, <4 x i8*>* %p0
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%g1 = load <4 x i8*>, <4 x i8*>* %p1
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%k = icmp eq <4 x i8*> %g0, %g1
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;CHECK: pcmpeqd
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%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
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ret <4 x i32> %j
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;CHECK: ret
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}
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