RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[AArch64] auto-generate complete test checks; NFC

Browse Source 
llvm-svn: 361908
This commit is contained in:
Sanjay Patel 2019-05-29 01:37:44 +00:00
parent f5773cac31
commit 7b2d16acaf
1 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
test/CodeGen/AArch64/sdag-store-merging-bug.ll
View File

@ -1,20 +1,22 @@
; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store -stop-after=instruction-select | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store | FileCheck %s
; Checks for a bug where selection dag store merging would construct wrong
; indices when extracting values from vectors, resulting in an invalid
; lane duplication in this case.
; The only way I could trigger stores with mismatching types getting merged was
; via the aarch64 slow-misaligned-128store code splitting stores earlier.
; CHECK-LABEL: name: func
; CHECK: LDRQui
; CHECK-NOT: INSERT_SUBREG
; CHECK-NOT: DUP
; CHECK-NEXT: STRQui
; aarch64 feature slow-misaligned-128store splits the following store.
; store merging immediately merges it back together (but used to get the
; merging wrong), this is the only way I was able to reproduce the bug...
define void @func(<2 x double>* %sptr, <2 x double>* %dptr) {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret
%load = load <2 x double>, <2 x double>* %sptr, align 8
; aarch64 feature slow-misaligned-128store splits the following store.
; store merging immediately merges it back together (but used to get the
; merging wrong), this is the only way I was able to reproduce the bug...
store <2 x double> %load, <2 x double>* %dptr, align 4
ret void
}