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[x86] enable machine combiner reassociations for 256-bit vector FP mul/add

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llvm-svn: 244705
This commit is contained in:
Sanjay Patel 2015-08-12 00:29:10 +00:00
parent 0ca30824f9
commit 7b4cd645e8
3 changed files with 66 additions and 2 deletions
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4
lib/Target/X86/X86InstrInfo.cpp
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@ -6401,10 +6401,14 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
case X86::MULSSrr:
case X86::VADDPDrr:
case X86::VADDPSrr:
case X86::VADDPDYrr:
case X86::VADDPSYrr:
case X86::VADDSDrr:
case X86::VADDSSrr:
case X86::VMULPDrr:
case X86::VMULPSrr:
case X86::VMULPDYrr:
case X86::VMULPSYrr:
case X86::VMULSDrr:
case X86::VMULSSrr:
return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;

60
test/CodeGen/X86/machine-combiner.ll
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@ -298,3 +298,63 @@ define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1,
ret <2 x double> %t2
}
; Verify that AVX 256-bit vector single-precison adds are reassociated.
define <8 x float> @reassociate_adds_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; AVX-LABEL: reassociate_adds_v8f32:
; AVX: # BB#0:
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vaddps %ymm3, %ymm2, %ymm1
; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = fmul <8 x float> %x0, %x1
%t1 = fadd <8 x float> %x2, %t0
%t2 = fadd <8 x float> %x3, %t1
ret <8 x float> %t2
}
; Verify that AVX 256-bit vector double-precison adds are reassociated.
define <4 x double> @reassociate_adds_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; AVX-LABEL: reassociate_adds_v4f64:
; AVX: # BB#0:
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vaddpd %ymm3, %ymm2, %ymm1
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = fmul <4 x double> %x0, %x1
%t1 = fadd <4 x double> %x2, %t0
%t2 = fadd <4 x double> %x3, %t1
ret <4 x double> %t2
}
; Verify that AVX 256-bit vector single-precison multiplies are reassociated.
define <8 x float> @reassociate_muls_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; AVX-LABEL: reassociate_muls_v8f32:
; AVX: # BB#0:
; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmulps %ymm3, %ymm2, %ymm1
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = fadd <8 x float> %x0, %x1
%t1 = fmul <8 x float> %x2, %t0
%t2 = fmul <8 x float> %x3, %t1
ret <8 x float> %t2
}
; Verify that AVX 256-bit vector double-precison multiplies are reassociated.
define <4 x double> @reassociate_muls_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; AVX-LABEL: reassociate_muls_v4f64:
; AVX: # BB#0:
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm3, %ymm2, %ymm1
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%t0 = fadd <4 x double> %x0, %x1
%t1 = fmul <4 x double> %x2, %t0
%t2 = fmul <4 x double> %x3, %t1
ret <4 x double> %t2
}

4
test/CodeGen/X86/sqrt-fastmath.ll
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@ -124,8 +124,8 @@ define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 {
; ESTIMATE-LABEL: reciprocal_square_root_v8f32:
; ESTIMATE: # BB#0:
; ESTIMATE-NEXT: vrsqrtps %ymm0, %ymm1
; ESTIMATE-NEXT: vmulps %ymm1, %ymm1, %ymm2
; ESTIMATE-NEXT: vmulps %ymm0, %ymm2, %ymm0
; ESTIMATE-NEXT: vmulps %ymm0, %ymm1, %ymm0
; ESTIMATE-NEXT: vmulps %ymm0, %ymm1, %ymm0
; ESTIMATE-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
; ESTIMATE-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
; ESTIMATE-NEXT: vmulps %ymm1, %ymm0, %ymm0