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Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>"
This reverts commit 5cd63e9ec2a385de2682949c0bbe928afaf35c91. https://bugs.llvm.org/show_bug.cgi?id=51707
This commit is contained in:
Tom Stellard
parent
b6614b2353
commit
7b93a88a1e
@ -103,8 +103,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder(G_BSWAP)
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.legalFor({s32, s64, v4s32, v2s32, v2s64})
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.clampScalar(0, s32, s64)
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.widenScalarToNextPow2(0)
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.customIf(typeIs(0, v2s16)); // custom lower as G_REV32 + G_LSHR
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.widenScalarToNextPow2(0);
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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.legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8})
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@ -799,8 +798,6 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_STORE:
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return legalizeLoadStore(MI, MRI, MIRBuilder, Observer);
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case TargetOpcode::G_BSWAP:
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return legalizeBSwap(MI, MRI, MIRBuilder);
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR:
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@ -1015,46 +1012,6 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
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return true;
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}
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bool AArch64LegalizerInfo::legalizeBSwap(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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assert(MI.getOpcode() == TargetOpcode::G_BSWAP);
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// The <2 x half> case needs special lowering because there isn't an
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// instruction that does that directly. Instead, we widen to <8 x i8>
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// and emit a G_REV32 followed by a G_LSHR knowing that instruction selection
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// will later match them as:
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//
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// rev32.8b v0, v0
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// ushr.2s v0, v0, #16
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//
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// We could emit those here directly, but it seems better to keep things as
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// generic as possible through legalization, and avoid committing layering
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// violations by legalizing & selecting here at the same time.
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Register ValReg = MI.getOperand(1).getReg();
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assert(LLT::fixed_vector(2, 16) == MRI.getType(ValReg));
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const LLT v2s32 = LLT::fixed_vector(2, 32);
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const LLT v8s8 = LLT::fixed_vector(8, 8);
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const LLT s32 = LLT::scalar(32);
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auto Undef = MIRBuilder.buildUndef(v8s8);
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auto Insert =
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MIRBuilder
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.buildInstr(TargetOpcode::INSERT_SUBREG, {v8s8}, {Undef, ValReg})
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.addImm(AArch64::ssub);
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auto Rev32 = MIRBuilder.buildInstr(AArch64::G_REV32, {v8s8}, {Insert});
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auto Bitcast = MIRBuilder.buildBitcast(v2s32, Rev32);
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auto Amt = MIRBuilder.buildConstant(v2s32, 16);
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auto UShr =
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MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {v2s32}, {Bitcast, Amt});
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auto Zero = MIRBuilder.buildConstant(s32, 0);
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auto Extract = MIRBuilder.buildExtractVectorElement(s32, UShr, Zero);
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MIRBuilder.buildBitcast({MI.getOperand(0).getReg()}, Extract);
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MI.eraseFromParent();
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return true;
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}
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bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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@ -35,8 +35,6 @@ public:
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MachineInstr &MI) const override;
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private:
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bool legalizeBSwap(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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@ -8,8 +8,6 @@
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define i16 @bswap_s16(i16 %a) { ret i16 0 }
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define <2 x i16> @bswap_2xi16(<2 x i16> %a) { ret <2 x i16> <i16 0, i16 0> }
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attributes #0 = { nounwind readnone speculatable willreturn }
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...
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@ -44,40 +42,3 @@ body: |
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RET_ReallyLR implicit $w0
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...
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---
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name: bswap_2xi16
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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liveins:
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- { reg: '$s0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $s0
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; CHECK-LABEL: name: bswap_2xi16
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
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; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:_(<8 x s8>) = INSERT_SUBREG [[DEF]](<8 x s8>), [[COPY]](<2 x s16>), %subreg.ssub
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; CHECK: [[REV32_:%[0-9]+]]:_(<8 x s8>) = G_REV32 [[INSERT_SUBREG]]
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; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[REV32_]](<8 x s8>)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[LSHR:%[0-9]+]]:_(<2 x s32>) = G_LSHR [[BITCAST]], [[BUILD_VECTOR]](<2 x s32>)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LSHR]](<2 x s32>), [[C1]](s64)
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; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[EVEC]](s32)
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; CHECK: $s0 = COPY [[BITCAST1]](<2 x s16>)
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; CHECK: RET_ReallyLR
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%0:_(<2 x s16>) = COPY $s0
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%1:_(<2 x s16>) = G_BSWAP %0
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$s0 = COPY %1(<2 x s16>)
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RET_ReallyLR
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...
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@ -555,8 +555,8 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_BSWAP (opcode {{[0-9]+}}): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_BITREVERSE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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