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Revert an un-intended change
llvm-svn: 28278
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@ -143,18 +143,6 @@ namespace llvm {
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class ScheduleDAG {
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public:
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// Scheduling heuristics
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enum SchedHeuristics {
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defaultScheduling, // Let the target specify its preference.
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noScheduling, // No scheduling, emit breadth first sequence.
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simpleScheduling, // Two pass, min. critical path, max. utilization.
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simpleNoItinScheduling, // Same as above exact using generic latency.
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listSchedulingBURR, // Bottom-up reg reduction list scheduling.
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listSchedulingTDRR, // Top-down reg reduction list scheduling.
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listSchedulingTD // Top-down list scheduler.
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};
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SelectionDAG &DAG; // DAG of the current basic block
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MachineBasicBlock *BB; // Current basic block
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const TargetMachine &TM; // Target processor
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@ -58,28 +58,39 @@ ViewSchedDAGs("view-sched-dags", cl::Hidden,
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static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
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#endif
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// Scheduling heuristics
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enum SchedHeuristics {
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defaultScheduling, // Let the target specify its preference.
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noScheduling, // No scheduling, emit breadth first sequence.
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simpleScheduling, // Two pass, min. critical path, max. utilization.
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simpleNoItinScheduling, // Same as above exact using generic latency.
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listSchedulingBURR, // Bottom-up reg reduction list scheduling.
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listSchedulingTDRR, // Top-down reg reduction list scheduling.
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listSchedulingTD // Top-down list scheduler.
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};
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namespace {
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cl::opt<ScheduleDAG::SchedHeuristics>
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cl::opt<SchedHeuristics>
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ISHeuristic(
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"sched",
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cl::desc("Choose scheduling style"),
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cl::init(ScheduleDAG::defaultScheduling),
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cl::init(defaultScheduling),
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cl::values(
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clEnumValN(ScheduleDAG::defaultScheduling, "default",
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clEnumValN(defaultScheduling, "default",
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"Target preferred scheduling style"),
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clEnumValN(ScheduleDAG::noScheduling, "none",
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clEnumValN(noScheduling, "none",
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"No scheduling: breadth first sequencing"),
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clEnumValN(ScheduleDAG::simpleScheduling, "simple",
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clEnumValN(simpleScheduling, "simple",
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"Simple two pass scheduling: minimize critical path "
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"and maximize processor utilization"),
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clEnumValN(ScheduleDAG::simpleNoItinScheduling, "simple-noitin",
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clEnumValN(simpleNoItinScheduling, "simple-noitin",
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"Simple two pass scheduling: Same as simple "
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"except using generic latency"),
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clEnumValN(ScheduleDAG::listSchedulingBURR, "list-burr",
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clEnumValN(listSchedulingBURR, "list-burr",
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"Bottom-up register reduction list scheduling"),
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clEnumValN(ScheduleDAG::listSchedulingTDRR, "list-tdrr",
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clEnumValN(listSchedulingTDRR, "list-tdrr",
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"Top-down register reduction list scheduling"),
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clEnumValN(ScheduleDAG::listSchedulingTD, "list-td",
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clEnumValN(listSchedulingTD, "list-td",
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"Top-down list scheduler"),
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clEnumValEnd));
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} // namespace
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@ -3409,7 +3420,7 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
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switch (ISHeuristic) {
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default: assert(0 && "Unrecognized scheduling heuristic");
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case ScheduleDAG::defaultScheduling:
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case defaultScheduling:
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
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SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
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else {
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@ -3418,22 +3429,22 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
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SL = createBURRListDAGScheduler(DAG, BB);
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}
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break;
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case ScheduleDAG::noScheduling:
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case noScheduling:
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SL = createBFS_DAGScheduler(DAG, BB);
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break;
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case ScheduleDAG::simpleScheduling:
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case simpleScheduling:
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SL = createSimpleDAGScheduler(false, DAG, BB);
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break;
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case ScheduleDAG::simpleNoItinScheduling:
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case simpleNoItinScheduling:
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SL = createSimpleDAGScheduler(true, DAG, BB);
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break;
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case ScheduleDAG::listSchedulingBURR:
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case listSchedulingBURR:
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SL = createBURRListDAGScheduler(DAG, BB);
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break;
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case ScheduleDAG::listSchedulingTDRR:
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case listSchedulingTDRR:
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SL = createTDRRListDAGScheduler(DAG, BB);
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break;
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case ScheduleDAG::listSchedulingTD:
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case listSchedulingTD:
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SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
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break;
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}
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