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[VE] Update shift operation instructions
Summary: Changing all mnemonic to match assembly instructions to simplify mnemonic naming rules. This time update all shift operation instructions. This also corrects instruction's operation kinds. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D78468
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
1792929a97
commit
7bb2a7f47f
@ -32,6 +32,10 @@ def uimm1 : Operand<i32>, PatLeaf<(imm), [{
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def uimm6 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<6>(N->getZExtValue()); }]>;
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// uimm7 - Generic immediate value.
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def uimm7 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<7>(N->getZExtValue()); }]>;
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// simm7 - Generic immediate value.
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def LO7 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
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@ -423,69 +427,27 @@ multiclass RRFm<string opcStr, bits<8>opc,
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RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, mOp, null_frag>,
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RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, mOp, null_frag>;
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// Multiclass for RR type instructions
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// Used by sra, sla, sll, and similar instructions
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// The order of operands are "$sx, $sz, $sy"
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// Generic RR multiclass for shift instructions with 2 arguments.
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// e.g. SLL, SRL, SLAWSX, and etc.
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let hasSideEffects = 0 in
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multiclass RRIm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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Operand immOp, Operand immOp2,
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SDPatternOperator OpNode = null_frag> {
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def rr : RR<
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opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),
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def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy"),
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[(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]> {
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let cy = 1;
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let cz = 1;
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let hasSideEffects = 0;
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}
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def ri : RR<
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opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy),
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[(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]>;
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let cz = 0 in
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def mr : RR<opc, (outs RC:$sx), (ins mimm:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy"),
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[(set Ty:$sx, (OpNode Ty:$sz, (i32 simm7:$sy)))]> {
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let cy = 0;
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let cz = 1;
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let hasSideEffects = 0;
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}
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def rm0 : RR<
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opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, (${sz})0, $sy")> {
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let cy = 1;
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let cz = 0;
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let sz{6} = 1;
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let hasSideEffects = 0;
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}
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def rm1 : RR<
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opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, (${sz})1, $sy")> {
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let cy = 1;
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let cz = 0;
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let hasSideEffects = 0;
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}
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def im0 : RR<
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opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy),
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!strconcat(opcStr, " $sx, (${sz})0, $sy")> {
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let cy = 0;
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let cz = 0;
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let sz{6} = 1;
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let hasSideEffects = 0;
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}
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def im1 : RR<
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opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy),
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!strconcat(opcStr, " $sx, (${sz})1, $sy")> {
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let cy = 0;
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let cz = 0;
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let hasSideEffects = 0;
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}
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def zi : RR<
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opc, (outs RC:$sx), (ins immOp:$sy),
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!strconcat(opcStr, " $sx, $sy"),
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[(set Ty:$sx, (OpNode 0, (i32 simm7:$sy)))]> {
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let cy = 0;
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let cz = 0;
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let sz = 0;
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let hasSideEffects = 0;
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}
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[(set Ty:$sx, (OpNode (Ty mimm:$sz), i32:$sy))]>;
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let cy = 0 in
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def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy"),
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[(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>;
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let cy = 0, cz = 0 in
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def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy"),
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[(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
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}
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// Generic RR multiclass with an argument.
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@ -898,23 +860,32 @@ let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>;
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let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>;
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let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>;
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// 5.3.2.4 Shift Instructions
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//-----------------------------------------------------------------------------
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// Section 8.6 - Shift Operation Instructions
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//-----------------------------------------------------------------------------
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let cx = 0 in
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defm SRAX : RRIm<"sra.l", 0x77, I64, i64, simm7, uimm6, sra>;
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let cx = 0 in
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defm SRA : RRIm<"sra.w.sx", 0x76, I32, i32, simm7, uimm6, sra>;
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let cx = 1 in
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defm SRAU : RRIm<"sra.w.zx", 0x76, I32, i32, simm7, uimm6>;
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// Section 8.6.1 - SLL (Shift Left Logical)
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defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
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let cx = 0 in
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defm SLL : RRIm<"sll", 0x65, I64, i64, simm7, uimm6, shl>;
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let cx = 0 in
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defm SLA : RRIm<"sla.w.sx", 0x66, I32, i32, simm7, uimm6, shl>;
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let cx = 1 in
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defm SLAU : RRIm<"sla.w.zx", 0x66, I32, i32, simm7, uimm6>;
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let cx = 0 in
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defm SRL : RRIm<"srl", 0x75, I64, i64, simm7, uimm6, srl>;
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// Section 8.6.2 - SLD (Shift Left Double)
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// Section 8.6.3 - SRL (Shift Right Logical)
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defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
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// Section 8.6.4 - SRD (Shift Right Double)
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// Section 8.6.5 - SLA (Shift Left Arithmetic)
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defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
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let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
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// Section 8.6.6 - SLAX (Shift Left Arithmetic)
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// Section 8.6.7 - SRA (Shift Right Arithmetic)
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defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
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let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;
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// Section 8.6.8 - SRAX (Shift Right Arithmetic)
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defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;
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def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
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(EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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@ -1113,27 +1084,27 @@ def : Pat<(f64 fpimm:$val),
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// Cast to i1
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def : Pat<(sext_inreg I32:$src, i1),
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(SRAri (SLAri $src, 31), 31)>;
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(SRAWSXri (SLAWSXri $src, 31), 31)>;
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def : Pat<(sext_inreg I64:$src, i1),
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(SRAXri (SLLri $src, 63), 63)>;
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(SRALri (SLLri $src, 63), 63)>;
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// Cast to i8
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def : Pat<(sext_inreg I32:$src, i8),
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(SRAri (SLAri $src, 24), 24)>;
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(SRAWSXri (SLAWSXri $src, 24), 24)>;
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def : Pat<(sext_inreg I64:$src, i8),
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(SRAXri (SLLri $src, 56), 56)>;
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(SRALri (SLLri $src, 56), 56)>;
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def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),
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(EXTRACT_SUBREG (SRAXri (SLLri $src, 56), 56), sub_i32)>;
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(EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;
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def : Pat<(and (trunc i64:$src), 0xff),
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(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>;
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// Cast to i16
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def : Pat<(sext_inreg I32:$src, i16),
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(SRAri (SLAri $src, 16), 16)>;
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(SRAWSXri (SLAWSXri $src, 16), 16)>;
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def : Pat<(sext_inreg I64:$src, i16),
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(SRAXri (SLLri $src, 48), 48)>;
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(SRALri (SLLri $src, 48), 48)>;
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def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),
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(EXTRACT_SUBREG (SRAXri (SLLri $src, 48), 48), sub_i32)>;
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(EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;
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def : Pat<(and (trunc i64:$src), 0xffff),
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(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>;
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@ -1553,7 +1524,7 @@ def : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>;
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def : Pat<(i64 (bitconvert f64:$src)), (COPY_TO_REGCLASS $src, I64)>;
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def : Pat<(i32 (bitconvert f32:$op)),
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(EXTRACT_SUBREG (SRAXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (SRALri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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$op, sub_f32), 32), sub_i32)>;
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def : Pat<(f32 (bitconvert i32:$op)),
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(EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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