[ARM] Add a batch of MVE integer instructions.

This includes integer arithmetic of various kinds (add/sub/multiply, saturating and not), and the immediate forms of VMOV and VMVN that load an immediate into all lanes of a vector. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62674 llvm-svn: 363936
2024-11-23 03:02:36 +01:00 · 2019-06-20 15:16:56 +00:00 · 2019-06-20 15:16:56 +00:00 · 7bde4ccbd2
commit 7bde4ccbd2
parent 2653a95667
5 changed files with 1127 additions and 1 deletions
--- a/lib/Target/ARM/ARMInstrMVE.td
+++ b/lib/Target/ARM/ARMInstrMVE.td
@ -1521,6 +1521,378 @@ def MVE_VMOV_to_lane_8     : MVE_VMOV_lane_8 <  "8", 0b0, MVE_VMOV_to_lane>;

 // end of mve_bit instructions

+// start of MVE Integer instructions
+
+class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class MVE_VMULt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<"vmul", suffix, size, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01001;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VMULt1i8  : MVE_VMULt1<"i8", 0b00>;
+def MVE_VMULt1i16 : MVE_VMULt1<"i16", 0b01>;
+def MVE_VMULt1i32 : MVE_VMULt1<"i32", 0b10>;
+
+class MVE_VQxDMULH<string iname, string suffix, bits<2> size, bit rounding,
+                  list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = rounding;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01011;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class MVE_VQDMULH<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_VQxDMULH<"vqdmulh", suffix, size, 0b0, pattern>;
+class MVE_VQRDMULH<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_VQxDMULH<"vqrdmulh", suffix, size, 0b1, pattern>;
+
+def MVE_VQDMULHi8   : MVE_VQDMULH<"s8",  0b00>;
+def MVE_VQDMULHi16  : MVE_VQDMULH<"s16", 0b01>;
+def MVE_VQDMULHi32  : MVE_VQDMULH<"s32", 0b10>;
+
+def MVE_VQRDMULHi8  : MVE_VQRDMULH<"s8",  0b00>;
+def MVE_VQRDMULHi16 : MVE_VQRDMULH<"s16", 0b01>;
+def MVE_VQRDMULHi32 : MVE_VQRDMULH<"s32", 0b10>;
+
+class MVE_VADDSUB<string iname, string suffix, bits<2> size, bit subtract,
+                    list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = subtract;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01000;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class MVE_VADD<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_VADDSUB<"vadd", suffix, size, 0b0, pattern>;
+class MVE_VSUB<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_VADDSUB<"vsub", suffix, size, 0b1, pattern>;
+
+def MVE_VADDi8  : MVE_VADD<"i8",  0b00>;
+def MVE_VADDi16 : MVE_VADD<"i16", 0b01>;
+def MVE_VADDi32 : MVE_VADD<"i32", 0b10>;
+
+def MVE_VSUBi8  : MVE_VSUB<"i8",  0b00>;
+def MVE_VSUBi16 : MVE_VSUB<"i16", 0b01>;
+def MVE_VSUBi32 : MVE_VSUB<"i32", 0b10>;
+
+class MVE_VQADDSUB<string iname, string suffix, bit U, bit subtract,
+                   bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{9} = subtract;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+class MVE_VQADD<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
+  : MVE_VQADDSUB<"vqadd", suffix, U, 0b0, size, pattern>;
+class MVE_VQSUB<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
+  : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size, pattern>;
+
+def MVE_VQADDs8  : MVE_VQADD<"s8",  0b0, 0b00>;
+def MVE_VQADDs16 : MVE_VQADD<"s16", 0b0, 0b01>;
+def MVE_VQADDs32 : MVE_VQADD<"s32", 0b0, 0b10>;
+def MVE_VQADDu8  : MVE_VQADD<"u8",  0b1, 0b00>;
+def MVE_VQADDu16 : MVE_VQADD<"u16", 0b1, 0b01>;
+def MVE_VQADDu32 : MVE_VQADD<"u32", 0b1, 0b10>;
+
+def MVE_VQSUBs8  : MVE_VQSUB<"s8",  0b0, 0b00>;
+def MVE_VQSUBs16 : MVE_VQSUB<"s16", 0b0, 0b01>;
+def MVE_VQSUBs32 : MVE_VQSUB<"s32", 0b0, 0b10>;
+def MVE_VQSUBu8  : MVE_VQSUB<"u8",  0b1, 0b00>;
+def MVE_VQSUBu16 : MVE_VQSUB<"u16", 0b1, 0b01>;
+def MVE_VQSUBu32 : MVE_VQSUB<"u32", 0b1, 0b10>;
+
+class MVE_VABD_int<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<"vabd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VABDs8  : MVE_VABD_int<"s8", 0b0, 0b00>;
+def MVE_VABDs16 : MVE_VABD_int<"s16", 0b0, 0b01>;
+def MVE_VABDs32 : MVE_VABD_int<"s32", 0b0, 0b10>;
+def MVE_VABDu8  : MVE_VABD_int<"u8", 0b1, 0b00>;
+def MVE_VABDu16 : MVE_VABD_int<"u16", 0b1, 0b01>;
+def MVE_VABDu32 : MVE_VABD_int<"u32", 0b1, 0b10>;
+
+class MVE_VRHADD<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<"vrhadd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00001;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VRHADDs8  : MVE_VRHADD<"s8", 0b0, 0b00>;
+def MVE_VRHADDs16 : MVE_VRHADD<"s16", 0b0, 0b01>;
+def MVE_VRHADDs32 : MVE_VRHADD<"s32", 0b0, 0b10>;
+def MVE_VRHADDu8  : MVE_VRHADD<"u8", 0b1, 0b00>;
+def MVE_VRHADDu16 : MVE_VRHADD<"u16", 0b1, 0b01>;
+def MVE_VRHADDu32 : MVE_VRHADD<"u32", 0b1, 0b10>;
+
+class MVE_VHADDSUB<string iname, string suffix, bit U, bit subtract,
+                   bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{9} = subtract;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class MVE_VHADD<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_VHADDSUB<"vhadd", suffix, U, 0b0, size, pattern>;
+class MVE_VHSUB<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
+
+def MVE_VHADDs8  : MVE_VHADD<"s8",  0b0, 0b00>;
+def MVE_VHADDs16 : MVE_VHADD<"s16", 0b0, 0b01>;
+def MVE_VHADDs32 : MVE_VHADD<"s32", 0b0, 0b10>;
+def MVE_VHADDu8  : MVE_VHADD<"u8",  0b1, 0b00>;
+def MVE_VHADDu16 : MVE_VHADD<"u16", 0b1, 0b01>;
+def MVE_VHADDu32 : MVE_VHADD<"u32", 0b1, 0b10>;
+
+def MVE_VHSUBs8  : MVE_VHSUB<"s8",  0b0, 0b00>;
+def MVE_VHSUBs16 : MVE_VHSUB<"s16", 0b0, 0b01>;
+def MVE_VHSUBs32 : MVE_VHSUB<"s32", 0b0, 0b10>;
+def MVE_VHSUBu8  : MVE_VHSUB<"u8",  0b1, 0b00>;
+def MVE_VHSUBu16 : MVE_VHSUB<"u16", 0b1, 0b01>;
+def MVE_VHSUBu32 : MVE_VHSUB<"u32", 0b1, 0b10>;
+
+class MVE_VDUP<string suffix, bit B, bit E, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins rGPR:$Rt), NoItinerary,
+          "vdup", suffix, "$Qd, $Rt", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Rt;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b101;
+  let Inst{22} = B;
+  let Inst{21-20} = 0b10;
+  let Inst{19-17} = Qd{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-12} = Rt;
+  let Inst{11-8} = 0b1011;
+  let Inst{7} = Qd{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = E;
+  let Inst{4-0} = 0b10000;
+}
+
+def MVE_VDUP32 : MVE_VDUP<"32", 0b0, 0b0>;
+def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1>;
+def MVE_VDUP8  : MVE_VDUP<"8",  0b1, 0b0>;
+
+class MVEIntSingleSrc<string iname, string suffix, bits<2> size,
+                         list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{19-18} = size{1-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class MVE_VCLSCLZ<string iname, string suffix, bits<2> size,
+                   bit count_zeroes, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00100;
+  let Inst{7} = count_zeroes;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VCLSs8  : MVE_VCLSCLZ<"vcls", "s8",  0b00, 0b0>;
+def MVE_VCLSs16 : MVE_VCLSCLZ<"vcls", "s16", 0b01, 0b0>;
+def MVE_VCLSs32 : MVE_VCLSCLZ<"vcls", "s32", 0b10, 0b0>;
+
+def MVE_VCLZs8  : MVE_VCLSCLZ<"vclz", "i8",  0b00, 0b1>;
+def MVE_VCLZs16 : MVE_VCLSCLZ<"vclz", "i16", 0b01, 0b1>;
+def MVE_VCLZs32 : MVE_VCLSCLZ<"vclz", "i32", 0b10, 0b1>;
+
+class MVE_VABSNEG_int<string iname, string suffix, bits<2> size, bit negate,
+                      list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b01;
+  let Inst{12-8} = 0b00011;
+  let Inst{7} = negate;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VABSs8  : MVE_VABSNEG_int<"vabs", "s8",  0b00, 0b0>;
+def MVE_VABSs16 : MVE_VABSNEG_int<"vabs", "s16", 0b01, 0b0>;
+def MVE_VABSs32 : MVE_VABSNEG_int<"vabs", "s32", 0b10, 0b0>;
+
+def MVE_VNEGs8  : MVE_VABSNEG_int<"vneg", "s8",  0b00, 0b1>;
+def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>;
+def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>;
+
+class MVE_VQABSNEG<string iname, string suffix, bits<2> size,
+                   bit negate, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00111;
+  let Inst{7} = negate;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VQABSs8  : MVE_VQABSNEG<"vqabs", "s8",  0b00, 0b0>;
+def MVE_VQABSs16 : MVE_VQABSNEG<"vqabs", "s16", 0b01, 0b0>;
+def MVE_VQABSs32 : MVE_VQABSNEG<"vqabs", "s32", 0b10, 0b0>;
+
+def MVE_VQNEGs8  : MVE_VQABSNEG<"vqneg", "s8",  0b00, 0b1>;
+def MVE_VQNEGs16 : MVE_VQABSNEG<"vqneg", "s16", 0b01, 0b1>;
+def MVE_VQNEGs32 : MVE_VQABSNEG<"vqneg", "s32", 0b10, 0b1>;
+
+class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
+                  dag iops, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
+          vpred_r, "", pattern> {
+  bits<13> imm;
+  bits<4> Qd;
+
+  let Inst{28} = imm{7};
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-19} = 0b000;
+  let Inst{18-16} = imm{6-4};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = 0b0;
+  let Inst{11-8} = cmode{3-0};
+  let Inst{7-6} = 0b01;
+  let Inst{5} = op;
+  let Inst{4} = 0b1;
+  let Inst{3-0} = imm{3-0};
+
+  let DecoderMethod = "DecodeMVEModImmInstruction";
+}
+
+let isReMaterializable = 1 in {
+let isAsCheapAsAMove = 1 in {
+def MVE_VMOVimmi8  : MVE_mod_imm<"vmov", "i8",  {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
+def MVE_VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def MVE_VMOVimmi32 : MVE_mod_imm<"vmov", "i32", {?,?,?,?}, 0b0, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+def MVE_VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm)>;
+def MVE_VMOVimmf32 : MVE_mod_imm<"vmov", "f32", {1,1,1,1}, 0b0, (ins nImmVMOVF32:$imm)>;
+} // let isAsCheapAsAMove = 1
+
+def MVE_VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def MVE_VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+} // let isReMaterializable = 1
+
+class MVE_VMINMAXA<string iname, string suffix, bits<2> size,
+                   bit bit_12, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111010;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def MVE_VMAXAs8  : MVE_VMINMAXA<"vmaxa", "s8",  0b00, 0b0>;
+def MVE_VMAXAs16 : MVE_VMINMAXA<"vmaxa", "s16", 0b01, 0b0>;
+def MVE_VMAXAs32 : MVE_VMINMAXA<"vmaxa", "s32", 0b10, 0b0>;
+
+def MVE_VMINAs8  : MVE_VMINMAXA<"vmina", "s8",  0b00, 0b1>;
+def MVE_VMINAs16 : MVE_VMINMAXA<"vmina", "s16", 0b01, 0b1>;
+def MVE_VMINAs32 : MVE_VMINMAXA<"vmina", "s32", 0b10, 0b1>;
+
+// end of MVE Integer instructions
+
 class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
  bits<3> fc;
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@ -5962,7 +5962,9 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
      !(hasMVE() &&
        (Mnemonic == "vmine" ||
         Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
-         Mnemonic == "vmvne" || Mnemonic == "vorne"))) {
+         Mnemonic == "vmvne" || Mnemonic == "vorne" ||
+         Mnemonic == "vnege" || Mnemonic == "vnegt" ||
+         Mnemonic.startswith("vq")))) {
    unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
    if (CC != ~0U) {
      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@ -310,6 +310,8 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
                               uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
@ -3422,6 +3424,35 @@ DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
  return S;
 }

+static DecodeStatus
+DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned imm = fieldFromInstruction(Insn, 0, 4);
+  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
+  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
+  imm |= cmode                             << 8;
+  imm |= fieldFromInstruction(Insn, 5, 1)  << 12;
+
+  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
+    return MCDisassembler::Fail;
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(imm));
+
+  Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+  Inst.addOperand(MCOperand::createReg(0));
+  Inst.addOperand(MCOperand::createImm(0));
+
+  return S;
+}
+
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
                                        uint64_t Address, const void *Decoder) {
  DecodeStatus S = MCDisassembler::Success;
--- a/test/MC/ARM/mve-integer.s
+++ b/test/MC/ARM/mve-integer.s
@ -0,0 +1,320 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=ERROR %s < %t
+
+# CHECK: vmov.i32 q0, #0x1bff  @ encoding: [0x81,0xef,0x5b,0x0c]
+vmov.i32 q0, #0x1bff
+
+# CHECK: vmov.i16 q0, #0x5c  @ encoding: [0x85,0xef,0x5c,0x08]
+vmov.i16 q0, #0x5c
+
+# CHECK: vmov.i8 q0, #0x4c  @ encoding: [0x84,0xef,0x5c,0x0e]
+vmov.i8 q0, #0x4c
+
+# CHECK: vmov.f32 q0, #-3.625000e+00  @ encoding: [0x80,0xff,0x5d,0x0f]
+vmov.f32 q0, #-3.625000e+00
+
+# CHECK: vmov.f32 q0, #1.250000e-01  @ encoding: [0x84,0xef,0x50,0x0f]
+vmov.f32 q0, #0.125
+
+# CHECK: vmov.f32 q0, #1.328125e-01  @ encoding: [0x84,0xef,0x51,0x0f]
+vmov.f32 q0, #0.1328125
+
+# CHECK: vmov.f32 q0, #3.100000e+01  @ encoding: [0x83,0xef,0x5f,0x0f]
+vmov.f32 q0, #31.0
+
+# CHECK: vmov.f32 s16, s1  @ encoding: [0xb0,0xee,0x60,0x8a]
+vmov.f32 s16, s1
+
+# CHECK: vmov.f64 d0, d1  @ encoding: [0xb0,0xee,0x41,0x0b]
+vmov.f64 d0, d1
+
+# CHECK: vmov.i64 q0, #0xff0000ffffffffff  @ encoding: [0x81,0xff,0x7f,0x0e]
+vmov.i64 q0, #0xff0000ffffffffff
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.i32 q0, #0xabcd
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.i16 q0, #0xabcd
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.i32 q0, #0xabffffff
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.i32 q0, #0xabffffff
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.f32 q0, #0.0625
+
+# ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
+vmov.f32 q0, #33.0
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+vmul.i8 q0, q0, q3
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+vmul.i16 q6, q0, q3
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+vmul.i32 q7, q3, q6
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+vqrdmulh.s8 q0, q5, q5
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+vqrdmulh.s16 q1, q4, q2
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+vqrdmulh.s32 q0, q5, q0
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+vqdmulh.s8 q0, q4, q5
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+vqdmulh.s16 q6, q4, q0
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+vqdmulh.s32 q5, q0, q6
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+vsub.i8 q3, q2, q5
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+vsub.i16 q0, q3, q6
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+vsub.i32 q0, q0, q6
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+vadd.i8 q0, q2, q2
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+vadd.i16 q2, q2, q1
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+vadd.i32 q0, q0, q6
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+vqsub.s8 q1, q6, q0
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+vqsub.s16 q0, q6, q1
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+vqsub.s32 q0, q0, q5
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+vqsub.u8 q0, q2, q6
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+vqsub.u16 q0, q7, q1
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+vqsub.u32 q1, q4, q7
+
+# CHECK: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
+vqadd.s8 q0, q1, q2
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+vqadd.s8 q0, q4, q6
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+vqadd.s16 q0, q5, q5
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+vqadd.s32 q0, q0, q4
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+vqadd.u8 q0, q4, q2
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+vqadd.u16 q4, q6, q6
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+vqadd.u32 q0, q1, q2
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+vabd.s8 q0, q0, q2
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+vabd.s16 q1, q5, q4
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+vabd.s32 q2, q3, q2
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+vabd.u8 q1, q6, q4
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+vabd.u16 q0, q6, q2
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+vabd.u32 q0, q7, q4
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+vrhadd.s8 q0, q1, q1
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+vrhadd.s16 q0, q1, q0
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+vrhadd.s32 q0, q4, q1
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+vrhadd.u8 q1, q0, q6
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+vrhadd.u16 q2, q2, q5
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+vrhadd.u32 q2, q3, q0
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+vhsub.s8 q0, q0, q2
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+vhsub.s16 q1, q3, q1
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+vhsub.s32 q0, q2, q5
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+vhsub.u8 q0, q4, q2
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+vhsub.u16 q0, q7, q5
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+vhsub.u32 q2, q6, q4
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+vhadd.s8 q0, q7, q0
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+vhadd.s16 q4, q0, q2
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+vhadd.s32 q0, q3, q1
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+vhadd.u8 q3, q0, q3
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+vhadd.u16 q0, q1, q3
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+vhadd.u32 q0, q1, q3
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+vdup.8 q6, r8
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+vdup.16 q7, lr
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+vdup.32 q1, r9
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+vpte.i8 eq, q0, q0
+vdupt.16 q0, r1
+vdupe.16 q0, r1
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+vcls.s8 q2, q1
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+vcls.s16 q0, q4
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+vcls.s32 q0, q0
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+vclz.i8 q0, q7
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+vclz.i16 q4, q7
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+vclz.i32 q7, q5
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+vneg.s8 q1, q0
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+vneg.s16 q0, q1
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+vneg.s32 q7, q2
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+vabs.s8 q1, q1
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+vabs.s16 q0, q2
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+vabs.s32 q0, q7
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+vqneg.s8 q0, q0
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+vqneg.s16 q6, q2
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+vqneg.s32 q7, q2
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+vqabs.s8 q2, q4
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+vqabs.s16 q0, q2
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+vqabs.s32 q0, q5
+
+vpste
+vnegt.s8 q0, q1
+vnege.s8 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+
+vpst
+vqaddt.s16 q0, q1, q2
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
+
+vpste
+vqnegt.s8 q0, q1
+vqnege.s16 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
+# CHECK: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOFP: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+vmina.s8 q1, q7
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOFP: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+vmina.s16 q1, q4
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOFP: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+vmina.s32 q0, q7
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOFP: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+vmaxa.s8 q0, q7
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+vmaxa.s16 q1, q0
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+vmaxa.s32 q1, q0
--- a/test/MC/Disassembler/ARM/mve-integer.txt
+++ b/test/MC/Disassembler/ARM/mve-integer.txt
@ -0,0 +1,401 @@
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2>%t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vmvn.i32 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x00]
+
+# CHECK: vmvn.i32 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x02]
+
+# CHECK: vmvn.i32 q0, #0x350000 @ encoding: [0x83,0xef,0x75,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x04]
+
+# CHECK: vmvn.i32 q0, #0x35000000 @ encoding: [0x83,0xef,0x75,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x06]
+
+# CHECK: vmvn.i16 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x08]
+
+# CHECK: vmvn.i16 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x0a]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0a]
+
+# CHECK: vmvn.i32 q0, #0x35ff @ encoding: [0x83,0xef,0x75,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0c]
+
+# CHECK: vmvn.i32 q0, #0x35ffff @ encoding: [0x83,0xef,0x75,0x0d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0d]
+
+# CHECK: vmov.i64 q0, #0xffff00ff00ff @ encoding: [0x83,0xef,0x75,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0e]
+
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0f]
+
+# CHECK: vmov.i32 q0, #0x1bff  @ encoding: [0x81,0xef,0x5b,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xef,0x5b,0x0c]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc0,0xef,0x50,0x00]
+
+# CHECK: vmov.i16 q0, #0x5c  @ encoding: [0x85,0xef,0x5c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x85,0xef,0x5c,0x08]
+
+# CHECK: vmov.i8 q0, #0x4c  @ encoding: [0x84,0xef,0x5c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xef,0x5c,0x0e]
+
+# CHECK: vmov.f32 q0, #-3.625000e+00  @ encoding: [0x80,0xff,0x5d,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xff,0x5d,0x0f]
+
+# CHECK: vmov.f32 q0, #1.000000e+00  @ encoding: [0x87,0xef,0x50,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x87,0xef,0x50,0x0f]
+
+# CHECK: vmov.f32 s16, s1  @ encoding: [0xb0,0xee,0x60,0x8a]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xee,0x60,0x8a]
+
+# CHECK: vmov.f64 d0, d1  @ encoding: [0xb0,0xee,0x41,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xee,0x41,0x0b]
+
+# CHECK: vmov.i64 q0, #0xff0000ffffffffff  @ encoding: [0x81,0xff,0x7f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xff,0x7f,0x0e]
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x56,0x09]
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x56,0xc9]
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x5c,0xe9]
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xff,0x4a,0x0b]
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xff,0x44,0x2b]
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xff,0x40,0x0b]
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x4a,0x0b]
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xef,0x40,0xcb]
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0xab]
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x4a,0x68]
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xff,0x4c,0x08]
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xff,0x4c,0x08]
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xef,0x44,0x08]
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x42,0x48]
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0x08]
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x50,0x22]
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xef,0x52,0x02]
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x5a,0x02]
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x5c,0x02]
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x52,0x02]
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x5e,0x22]
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x5c,0x00]
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x5a,0x00]
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x58,0x00]
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x54,0x00]
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x5c,0x80]
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x54,0x00]
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x07]
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x48,0x27]
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x44,0x47]
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xff,0x48,0x27]
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x44,0x07]
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xff,0x48,0x07]
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xef,0x42,0x01]
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x40,0x01]
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xef,0x42,0x01]
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x4c,0x21]
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xff,0x4a,0x41]
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xff,0x40,0x41]
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x02]
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xef,0x42,0x22]
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xef,0x4a,0x02]
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x44,0x02]
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x4a,0x02]
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xff,0x48,0x42]
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xef,0x40,0x00]
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x44,0x80]
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x42,0x00]
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x46,0x60]
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x46,0x00]
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x46,0x00]
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x10,0x8b]
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xae,0xee,0x30,0xeb]
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xee,0x10,0x9b]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xa0,0xee,0x30,0x1b]
+[0xa0,0xee,0x30,0x1b]
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x42,0x44]
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x48,0x04]
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x40,0x04]
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xce,0x04]
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xce,0x84]
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xca,0xe4]
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0xc0,0x23]
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0xc2,0x03]
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0xc4,0xe3]
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0x42,0x23]
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0x44,0x03]
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0x4e,0x03]
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xc0,0x07]
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xc4,0xc7]
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xc4,0xe7]
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x48,0x47]
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x44,0x07]
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x4a,0x07]
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x3e]
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x89,0x3e]
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x8f,0x1e]
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x0e]
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x81,0x2e]
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x81,0x2e]