RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

[GISel]: New Opcode G_FLOG/G_FLOG2

Browse Source 
https://reviews.llvm.org/D34837

llvm-svn: 306766
This commit is contained in:
Aditya Nandakumar 2017-06-29 23:43:44 +00:00
parent 92bf1f9f72
commit 7c00869517
5 changed files with 51 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
include/llvm/Target/GenericOpcodes.td
View File

@ -429,6 +429,21 @@ def G_FEXP2 : Instruction {
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
// Floating point base-2 logarithm of a value.
def G_FLOG : Instruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
// Floating point base-2 logarithm of a value.
def G_FLOG2 : Instruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------

1
include/llvm/Target/GlobalISel/SelectionDAGCompat.td
View File

@ -63,6 +63,7 @@ def : GINodeEquiv<G_FDIV, fdiv>;
def : GINodeEquiv<G_FREM, frem>;
def : GINodeEquiv<G_FPOW, fpow>;
def : GINodeEquiv<G_FEXP2, fexp2>;
def : GINodeEquiv<G_FLOG2, flog2>;
def : GINodeEquiv<G_BR, br>;
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.

6
include/llvm/Target/TargetOpcodes.def
View File

@ -375,6 +375,12 @@ HANDLE_TARGET_OPCODE(G_FEXP)
/// Generic base-2 exponential of a value.
HANDLE_TARGET_OPCODE(G_FEXP2)
/// Floating point base-e logarithm of a value.
HANDLE_TARGET_OPCODE(G_FLOG)
/// Floating point base-2 logarithm of a value.
HANDLE_TARGET_OPCODE(G_FLOG2)
/// Generic FP negation.
HANDLE_TARGET_OPCODE(G_FNEG)

10
lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -730,6 +730,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::log:
MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::log2:
MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::fma:
MIRBuilder.buildInstr(TargetOpcode::G_FMA)
.addDef(getOrCreateVReg(CI))

19
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -1291,6 +1291,25 @@ define float @test_exp2_intrin(float %a) {
ret float %res
}
declare float @llvm.log.f32(float)
define float @test_log_intrin(float %a) {
; CHECK-LABEL: name: test_log_intrin
; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG [[A]]
; CHECK: %s0 = COPY [[RES]]
%res = call float @llvm.log.f32(float %a)
ret float %res
}
declare float @llvm.log2.f32(float)
define float @test_log2_intrin(float %a) {
; CHECK-LABEL: name: test_log2_intrin
; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG2 [[A]]
; CHECK: %s0 = COPY [[RES]]
%res = call float @llvm.log2.f32(float %a)
ret float %res
}
declare void @llvm.lifetime.start.p0i8(i64, i8*)
declare void @llvm.lifetime.end.p0i8(i64, i8*)
define void @test_lifetime_intrin() {