RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

ARM: make sure ARM-mode pseudo-inst requires IsARM

Browse Source 
I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.

rdar://problem/14817358

llvm-svn: 189096
This commit is contained in:
Tim Northover 2013-08-23 10:16:39 +00:00
parent c6286de5e8
commit 7c24b95efe
2 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -4197,7 +4197,7 @@ def MOVCCi32imm
8, IIC_iCMOVix2,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
cmovpred:$p))]>,
RegConstraint<"$false = $Rd">, Requires<[HasV6T2]>;
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
let isMoveImm = 1 in
def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),

11
test/CodeGen/Thumb2/thumb2-select.ll
View File

@ -99,8 +99,17 @@ entry:
define i32 @f10(i32 %a, i32 %b) {
; CHECK-LABEL: f10:
; CHECK: movwne r2, #1234 @ encoding: [0x40,0xf2,0xd2,0x42]
; CHECK: movwne {{r[0-9]+}}, #1234 @ encoding: [0x40,0xf2,0xd2,0x4{{[0-9a-f]+}}]
%tst = icmp ne i32 %a, %b
%val = select i1 %tst, i32 1234, i32 12345
ret i32 %val
}
; Make sure we pick the Thumb encoding for movw/movt
define i32 @f11(i32 %a, i32 %b) {
; CHECK-LABEL: f11:
; CHECK: movwne {{r[0-9]+}}, #50033 @ encoding: [0x4c,0xf2,0x71,0x3{{[0-9a-f]+}}]
%tst = icmp ne i32 %a, %b
%val = select i1 %tst, i32 123454321, i32 543212345
ret i32 %val
}