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[InstSimplify] add tests for PR27689; regenerate checks
llvm-svn: 273128
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3302aab6a9
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@ -1,9 +1,9 @@
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; NOTE: Assertions have been autogenerated by update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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define i64 @pow2(i32 %x) {
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; CHECK-LABEL: @pow2(
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; CHECK: [[NEGX:%.*]] = sub i32 0, %x
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; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, %x
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; CHECK-NEXT: [[X2:%.*]] = and i32 %x, [[NEGX]]
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; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64
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; CHECK-NEXT: ret i64 [[E]]
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@ -18,7 +18,7 @@ define i64 @pow2(i32 %x) {
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define i64 @pow2b(i32 %x) {
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; CHECK-LABEL: @pow2b(
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; CHECK: [[SH:%.*]] = shl i32 2, %x
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; CHECK-NEXT: [[SH:%.*]] = shl i32 2, %x
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; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
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; CHECK-NEXT: ret i64 [[E]]
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;
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@ -31,7 +31,7 @@ define i64 @pow2b(i32 %x) {
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define i32 @sub_neg_nuw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_neg_nuw(
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; CHECK: ret i32 %x
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; CHECK-NEXT: ret i32 %x
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;
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%neg = sub nuw i32 0, %y
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%sub = sub i32 %x, %neg
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@ -40,7 +40,7 @@ define i32 @sub_neg_nuw(i32 %x, i32 %y) {
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define i1 @and_of_icmps0(i32 %b) {
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; CHECK-LABEL: @and_of_icmps0(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add i32 %b, 2
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%2 = icmp ult i32 %1, 4
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@ -51,7 +51,7 @@ define i1 @and_of_icmps0(i32 %b) {
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define i1 @and_of_icmps1(i32 %b) {
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; CHECK-LABEL: @and_of_icmps1(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp slt i32 %1, 4
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@ -62,7 +62,7 @@ define i1 @and_of_icmps1(i32 %b) {
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define i1 @and_of_icmps2(i32 %b) {
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; CHECK-LABEL: @and_of_icmps2(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add i32 %b, 2
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%2 = icmp ule i32 %1, 3
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@ -73,7 +73,7 @@ define i1 @and_of_icmps2(i32 %b) {
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define i1 @and_of_icmps3(i32 %b) {
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; CHECK-LABEL: @and_of_icmps3(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sle i32 %1, 3
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@ -84,7 +84,7 @@ define i1 @and_of_icmps3(i32 %b) {
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define i1 @and_of_icmps4(i32 %b) {
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; CHECK-LABEL: @and_of_icmps4(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ult i32 %1, 4
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@ -95,7 +95,7 @@ define i1 @and_of_icmps4(i32 %b) {
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define i1 @and_of_icmps5(i32 %b) {
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; CHECK-LABEL: @and_of_icmps5(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ule i32 %1, 3
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@ -106,7 +106,7 @@ define i1 @and_of_icmps5(i32 %b) {
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define i1 @or_of_icmps0(i32 %b) {
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; CHECK-LABEL: @or_of_icmps0(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add i32 %b, 2
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%2 = icmp uge i32 %1, 4
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@ -117,7 +117,7 @@ define i1 @or_of_icmps0(i32 %b) {
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define i1 @or_of_icmps1(i32 %b) {
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; CHECK-LABEL: @or_of_icmps1(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sge i32 %1, 4
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@ -128,7 +128,7 @@ define i1 @or_of_icmps1(i32 %b) {
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define i1 @or_of_icmps2(i32 %b) {
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; CHECK-LABEL: @or_of_icmps2(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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@ -139,7 +139,7 @@ define i1 @or_of_icmps2(i32 %b) {
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define i1 @or_of_icmps3(i32 %b) {
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; CHECK-LABEL: @or_of_icmps3(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nsw i32 %b, 2
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%2 = icmp sgt i32 %1, 3
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@ -150,7 +150,7 @@ define i1 @or_of_icmps3(i32 %b) {
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define i1 @or_of_icmps4(i32 %b) {
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; CHECK-LABEL: @or_of_icmps4(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp uge i32 %1, 4
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@ -161,7 +161,7 @@ define i1 @or_of_icmps4(i32 %b) {
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define i1 @or_of_icmps5(i32 %b) {
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; CHECK-LABEL: @or_of_icmps5(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = add nuw i32 %b, 2
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%2 = icmp ugt i32 %1, 3
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@ -172,7 +172,7 @@ define i1 @or_of_icmps5(i32 %b) {
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define i32 @neg_nuw(i32 %x) {
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; CHECK-LABEL: @neg_nuw(
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; CHECK: ret i32 0
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; CHECK-NEXT: ret i32 0
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;
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%neg = sub nuw i32 0, %x
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ret i32 %neg
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@ -180,7 +180,7 @@ define i32 @neg_nuw(i32 %x) {
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define i1 @and_icmp1(i32 %x, i32 %y) {
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; CHECK-LABEL: @and_icmp1(
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; CHECK: [[TMP1:%.*]] = icmp ult i32 %x, %y
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %x, %y
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp ult i32 %x, %y
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@ -191,7 +191,7 @@ define i1 @and_icmp1(i32 %x, i32 %y) {
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define i1 @and_icmp2(i32 %x, i32 %y) {
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; CHECK-LABEL: @and_icmp2(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%1 = icmp ult i32 %x, %y
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%2 = icmp eq i32 %y, 0
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@ -201,7 +201,7 @@ define i1 @and_icmp2(i32 %x, i32 %y) {
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define i1 @or_icmp1(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp1(
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; CHECK: [[TMP1:%.*]] = icmp ne i32 %y, 0
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %y, 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp ult i32 %x, %y
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@ -212,7 +212,7 @@ define i1 @or_icmp1(i32 %x, i32 %y) {
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define i1 @or_icmp2(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp2(
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; CHECK: ret i1 true
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; CHECK-NEXT: ret i1 true
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;
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%1 = icmp uge i32 %x, %y
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%2 = icmp ne i32 %y, 0
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@ -222,7 +222,7 @@ define i1 @or_icmp2(i32 %x, i32 %y) {
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define i1 @or_icmp3(i32 %x, i32 %y) {
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; CHECK-LABEL: @or_icmp3(
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; CHECK: [[TMP1:%.*]] = icmp uge i32 %x, %y
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 %x, %y
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = icmp uge i32 %x, %y
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@ -231,3 +231,37 @@ define i1 @or_icmp3(i32 %x, i32 %y) {
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ret i1 %3
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}
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define i32 @and_of_zexted_icmps(i32 %i) {
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; CHECK-LABEL: @and_of_zexted_icmps(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %i, 0
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; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %i, 4
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; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[CONV]], [[CONV2]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%cmp = icmp eq i32 %i, 0
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%conv = zext i1 %cmp to i32
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%cmp1 = icmp ugt i32 %i, 4
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%conv2 = zext i1 %cmp1 to i32
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%and = and i32 %conv, %conv2
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ret i32 %and
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}
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define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
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; CHECK-LABEL: @and_of_zexted_icmps_vec(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> %i, zeroinitializer
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; CHECK-NEXT: [[CONV:%.*]] = zext <4 x i1> [[CMP]] to <4 x i32>
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <4 x i32> %i, zeroinitializer
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; CHECK-NEXT: [[CONV2:%.*]] = zext <4 x i1> [[CMP1]] to <4 x i32>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[CONV]], [[CONV2]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%cmp = icmp eq <4 x i32> %i, zeroinitializer
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%conv = zext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp slt <4 x i32> %i, zeroinitializer
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%conv2 = zext <4 x i1> %cmp1 to <4 x i32>
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%and = and <4 x i32> %conv, %conv2
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ret <4 x i32> %and
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}
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