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[RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.

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This avoids being dependent on SimplifyDemandedBits having cleared
those bits.

It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.
This commit is contained in:
Craig Topper 2021-01-24 00:13:12 -08:00
parent cc37457339
commit 7c6fbeb405
1 changed files with 1 additions and 1 deletions
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lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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@ -871,7 +871,7 @@ bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
// Immediate range should be enforced by uimm5 predicate.
assert(VC2 < 32 && "Unexpected immediate");
return VC1 == ((uint64_t)0xFFFFFFFF << VC2);
return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF);
}
bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {