RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Add predicate for AArch64 crypto instructions.

Browse Source 
llvm-svn: 195071
This commit is contained in:
Jiangning Liu 2013-11-19 01:38:31 +00:00
parent 8bb31d387d
commit 7c858f236d
3 changed files with 14 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -7605,6 +7605,7 @@ class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
(v16i8 VPR128:$Rn))))],
NoItinerary>{
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
@ -7632,6 +7633,7 @@ class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
(v4i32 VPR128:$Rn))))],
NoItinerary> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
@ -7646,7 +7648,9 @@ class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
asmop # "\t$Rd, $Rn",
[(set (v1i32 FPR32:$Rd),
(v1i32 (opnode (v1i32 FPR32:$Rn))))],
NoItinerary>;
NoItinerary> {
let Predicates = [HasNEON, HasCrypto];
}
def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
@ -7662,6 +7666,7 @@ class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
@ -7681,6 +7686,7 @@ class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
@ -7700,6 +7706,7 @@ class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
let Predicates = [HasNEON, HasCrypto];
}
def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;

4
test/CodeGen/AArch64/neon-crypto.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
@ -31,6 +32,7 @@ declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1
define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
; CHECK: test_vaeseq_u8:
; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
; CHECK-NO-CRYPTO: Cannot select: intrinsic %llvm.arm.neon.aese
entry:
%aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %aese.i

4
test/MC/AArch64/neon-crypto.s
View File

@ -1,4 +1,5 @@
// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s
// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s
// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s
// Check that the assembler can handle the documented syntax for AArch64
@ -11,6 +12,7 @@
aesmc v0.16b, v1.16b
aesimc v0.16b, v1.16b
// CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled
// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]
// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]
// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]