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Implement floating point to integer conversion in mips fast-isel
Summary: Add the ability to convert 64 or 32 bit floating point values to integer in mips fast-isel Test Plan: fpintconv.ll ran 4 flavors of test-suite with no errors, misp32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5562 llvm-svn: 219511
This commit is contained in:
Reed Kotler
parent
9cbee3a665
commit
7c9f20a7a1
@ -48,6 +48,7 @@ class MipsFastISel final : public FastISel {
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LLVMContext *Context;
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bool TargetSupported;
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bool UnsupportedFPMode;
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public:
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explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
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@ -63,6 +64,7 @@ public:
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TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
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((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
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(Subtarget->isABI_O32())));
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UnsupportedFPMode = Subtarget->isFP64bit();
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}
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bool fastSelectInstruction(const Instruction *I) override;
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@ -82,6 +84,7 @@ private:
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bool SelectTrunc(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectFPToI(const Instruction *I, bool IsSigned);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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@ -191,11 +194,15 @@ bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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break;
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}
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case MVT::f32: {
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if (UnsupportedFPMode)
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return false;
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ResultReg = createResultReg(&Mips::FGR32RegClass);
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Opc = Mips::LWC1;
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break;
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}
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case MVT::f64: {
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if (UnsupportedFPMode)
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return false;
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ResultReg = createResultReg(&Mips::AFGR64RegClass);
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Opc = Mips::LDC1;
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break;
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@ -218,7 +225,7 @@ unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return MaterializeFP(CFP, VT);
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return (UnsupportedFPMode) ? 0 : MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return MaterializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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@ -244,9 +251,13 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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Opc = Mips::SW;
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break;
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case MVT::f32:
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if (UnsupportedFPMode)
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return false;
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Opc = Mips::SWC1;
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break;
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case MVT::f64:
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if (UnsupportedFPMode)
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return false;
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Opc = Mips::SDC1;
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break;
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default:
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@ -388,6 +399,8 @@ bool MipsFastISel::SelectRet(const Instruction *I) {
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// Attempt to fast-select a floating-point extend instruction.
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bool MipsFastISel::SelectFPExt(const Instruction *I) {
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if (UnsupportedFPMode)
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return false;
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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@ -409,6 +422,8 @@ bool MipsFastISel::SelectFPExt(const Instruction *I) {
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// Attempt to fast-select a floating-point truncate instruction.
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bool MipsFastISel::SelectFPTrunc(const Instruction *I) {
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if (UnsupportedFPMode)
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return false;
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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@ -481,6 +496,53 @@ bool MipsFastISel::SelectTrunc(const Instruction *I) {
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return true;
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}
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// Attempt to fast-select a floating-point-to-integer conversion.
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bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
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if (UnsupportedFPMode)
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return false;
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MVT DstVT, SrcVT;
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if (!IsSigned)
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return false; // We don't handle this case yet. There is no native
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// instruction for this but it can be synthesized.
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Type *DstTy = I->getType();
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if (!isTypeLegal(DstTy, DstVT))
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return false;
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if (DstVT != MVT::i32)
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return false;
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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if (!isTypeLegal(SrcTy, SrcVT))
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return false;
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if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (SrcReg == 0)
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return false;
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// Determine the opcode for the conversion, which takes place
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// entirely within FPRs.
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unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
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unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
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unsigned Opc;
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if (SrcVT == MVT::f32)
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Opc = Mips::TRUNC_W_S;
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else
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Opc = Mips::TRUNC_W_D32;
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// Generate the convert.
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EmitInst(Opc, TempReg).addReg(SrcReg);
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EmitInst(Mips::MFC1, DestReg).addReg(TempReg);
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updateValueMap(I, DestReg);
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return true;
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}
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bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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if (!TargetSupported)
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return false;
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@ -502,11 +564,17 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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return SelectFPTrunc(I);
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case Instruction::FPExt:
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return SelectFPExt(I);
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case Instruction::FPToSI:
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return SelectFPToI(I, /*isSigned*/ true);
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case Instruction::FPToUI:
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return SelectFPToI(I, /*isSigned*/ false);
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}
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return false;
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}
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unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
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if (UnsupportedFPMode)
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return 0;
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int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
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if (VT == MVT::f32) {
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const TargetRegisterClass *RC = &Mips::FGR32RegClass;
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35
test/CodeGen/Mips/Fast-ISel/fpintconv.ll
Normal file
35
test/CodeGen/Mips/Fast-ISel/fpintconv.ll
Normal file
@ -0,0 +1,35 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@f = global float 0x40D6E83280000000, align 4
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@d = global double 0x4132D68780000000, align 8
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@i_f = common global i32 0, align 4
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@i_d = common global i32 0, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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; Function Attrs: nounwind
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define void @ifv() {
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entry:
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; CHECK-LABEL: .ent ifv
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%0 = load float* @f, align 4
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%conv = fptosi float %0 to i32
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; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}}
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; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
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store i32 %conv, i32* @i_f, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @idv() {
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entry:
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; CHECK-LABEL: .ent idv
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%0 = load double* @d, align 8
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%conv = fptosi double %0 to i32
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; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}}
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; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
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store i32 %conv, i32* @i_d, align 4
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ret void
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}
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