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[M68k] Allow user to preserve certain registers
Add `-ffixed-a[0-6]` and `-ffixed-d[0-7]` and the corresponding subtarget features to prevent certain register from being allocated. Differential Revision: https://reviews.llvm.org/D102805
This commit is contained in:
Min-Yih Hsu
parent
528de0554b
commit
7cd0b2d7ab
@ -47,6 +47,15 @@ def FeatureISA60
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"Is M68060 ISA supported",
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[ FeatureISA40 ]>;
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foreach i = {0-6} in
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def FeatureReserveA#i :
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SubtargetFeature<"reserve-a"#i, "UserReservedRegister[M68k::A"#i#"]",
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"true", "Reserve A"#i#" register">;
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foreach i = {0-7} in
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def FeatureReserveD#i :
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SubtargetFeature<"reserve-d"#i, "UserReservedRegister[M68k::D"#i#"]",
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"true", "Reserve D"#i#" register">;
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//===----------------------------------------------------------------------===//
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// M68k processors supported.
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//===----------------------------------------------------------------------===//
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@ -133,6 +133,12 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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}
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};
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// Registers reserved by users
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for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {
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if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))
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setBitVector(Reg);
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}
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setBitVector(M68k::PC);
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setBitVector(M68k::SP);
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@ -47,7 +47,8 @@ void M68kSubtarget::anchor() {}
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M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const M68kTargetMachine &TM)
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: M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
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: M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
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UserReservedRegister(M68k::NUM_TARGET_REGS), TM(TM), TSInfo(),
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InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
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FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
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TargetTriple(TT) {}
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@ -18,6 +18,7 @@
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#include "M68kISelLowering.h"
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#include "M68kInstrInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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@ -47,6 +48,8 @@ protected:
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enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
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SubtargetEnum SubtargetKind = M00;
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BitVector UserReservedRegister;
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InstrItineraryData InstrItins;
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/// Small section is used.
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@ -95,6 +98,11 @@ public:
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bool isPositionIndependent() const;
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bool isRegisterReservedByUser(Register R) const {
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assert(R < M68k::NUM_TARGET_REGS && "Register out of range");
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return UserReservedRegister[R];
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}
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/// Classify a global variable reference for the current subtarget according
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/// to how we should reference it in a non-pcrel context.
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unsigned char classifyLocalReference(const GlobalValue *GV) const;
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70
test/CodeGen/M68k/reserved-regs.ll
Normal file
70
test/CodeGen/M68k/reserved-regs.ll
Normal file
@ -0,0 +1,70 @@
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; RUN: llc -mtriple=m68k -mattr="+reserve-a0" < %s | FileCheck --check-prefix=A0 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a1" < %s | FileCheck --check-prefix=A1 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a2" < %s | FileCheck --check-prefix=A2 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a3" < %s | FileCheck --check-prefix=A3 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a4" < %s | FileCheck --check-prefix=A4 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a5" < %s | FileCheck --check-prefix=A5 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-a6" < %s | FileCheck --check-prefix=A6 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d0" < %s | FileCheck --check-prefix=D0 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d1" < %s | FileCheck --check-prefix=D1 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d2" < %s | FileCheck --check-prefix=D2 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d3" < %s | FileCheck --check-prefix=D3 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d4" < %s | FileCheck --check-prefix=D4 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d5" < %s | FileCheck --check-prefix=D5 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d6" < %s | FileCheck --check-prefix=D6 %s
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; RUN: llc -mtriple=m68k -mattr="+reserve-d7" < %s | FileCheck --check-prefix=D7 %s
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; Used to exhaust all registers
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;
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; A better way to do this might be:
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; ```
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; @var = global [16 x i32] zeroinitializer
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; ...
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; %tmp = load load volatile [16 x i32], [16 x i32]* @var
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; store volatile [16 x i32] %tmp, [16 x i32]* @var
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; ```
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; Which is copied from `test/CodeGen/RISCV/reserved-regs.ll`.
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; But currently we have problem doing codegen for the above snippet
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; (https://bugs.llvm.org/show_bug.cgi?id=50377).
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define void @foo(i32* nocapture readonly %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32* nocapture readonly %d,
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i32* nocapture readonly %a1, i32* nocapture readonly %b1, i32* nocapture readonly %c1, i32* nocapture readonly %d1,
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i32* nocapture readonly %a2, i32* nocapture readonly %b2, i32* nocapture readonly %c2, i32* nocapture readonly %d2,
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i32* nocapture readonly %a3, i32* nocapture readonly %b3, i32* nocapture readonly %c3, i32* nocapture readonly %d3) {
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entry:
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%0 = load i32, i32* %a, align 4
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%1 = load i32, i32* %b, align 4
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%2 = load i32, i32* %c, align 4
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%3 = load i32, i32* %d, align 4
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%4 = load i32, i32* %a1, align 4
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%5 = load i32, i32* %b1, align 4
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%6 = load i32, i32* %c1, align 4
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%7 = load i32, i32* %d1, align 4
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%8 = load i32, i32* %a2, align 4
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%9 = load i32, i32* %b2, align 4
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%10 = load i32, i32* %c2, align 4
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%11 = load i32, i32* %d2, align 4
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%12 = load i32, i32* %a3, align 4
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%13 = load i32, i32* %b3, align 4
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%14 = load i32, i32* %c3, align 4
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%15 = load i32, i32* %d3, align 4
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; A0-NOT: %a0
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; A1-NOT: %a1
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; A2-NOT: %a2
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; A3-NOT: %a3
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; A4-NOT: %a4
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; A5-NOT: %a5
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; A6-NOT: %a6
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; D0-NOT: %d0
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; D1-NOT: %d1
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; D2-NOT: %d2
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; D3-NOT: %d3
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; D4-NOT: %d4
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; D5-NOT: %d5
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; D6-NOT: %d6
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; D7-NOT: %d7
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tail call void @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15)
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ret void
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}
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declare void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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