RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

[X86] Remove isel patterns for selecting tzcnt/lzcnt from cmove/ne+cttz/ctlz. These are folded by DAG combine now.

Browse Source 
llvm-svn: 267326
This commit is contained in:
Craig Topper 2016-04-24 04:38:34 +00:00
parent 370802b1a1
commit 7cda2fdad5
1 changed files with 0 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
lib/Target/X86/X86InstrInfo.td
View File

@ -2165,46 +2165,6 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
(implicit EFLAGS)]>, XS;
}
let Predicates = [HasLZCNT] in {
def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E),
(X86cmp GR16:$src, (i16 0))),
(LZCNT16rr GR16:$src)>;
def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E),
(X86cmp GR32:$src, (i32 0))),
(LZCNT32rr GR32:$src)>;
def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E),
(X86cmp GR64:$src, (i64 0))),
(LZCNT64rr GR64:$src)>;
def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_NE),
(X86cmp GR16:$src, (i16 0))),
(LZCNT16rr GR16:$src)>;
def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_NE),
(X86cmp GR32:$src, (i32 0))),
(LZCNT32rr GR32:$src)>;
def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_NE),
(X86cmp GR64:$src, (i64 0))),
(LZCNT64rr GR64:$src)>;
def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
(X86cmp (loadi16 addr:$src), (i16 0))),
(LZCNT16rm addr:$src)>;
def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
(X86cmp (loadi32 addr:$src), (i32 0))),
(LZCNT32rm addr:$src)>;
def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
(X86cmp (loadi64 addr:$src), (i64 0))),
(LZCNT64rm addr:$src)>;
def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_NE),
(X86cmp (loadi16 addr:$src), (i16 0))),
(LZCNT16rm addr:$src)>;
def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_NE),
(X86cmp (loadi32 addr:$src), (i32 0))),
(LZCNT32rm addr:$src)>;
def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_NE),
(X86cmp (loadi64 addr:$src), (i64 0))),
(LZCNT64rm addr:$src)>;
}
//===----------------------------------------------------------------------===//
// BMI Instructions
//
@ -2281,46 +2241,6 @@ let Predicates = [HasBMI] in {
(BLSI64rr GR64:$src)>;
}
let Predicates = [HasBMI] in {
def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E),
(X86cmp GR16:$src, (i16 0))),
(TZCNT16rr GR16:$src)>;
def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E),
(X86cmp GR32:$src, (i32 0))),
(TZCNT32rr GR32:$src)>;
def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E),
(X86cmp GR64:$src, (i64 0))),
(TZCNT64rr GR64:$src)>;
def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_NE),
(X86cmp GR16:$src, (i16 0))),
(TZCNT16rr GR16:$src)>;
def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_NE),
(X86cmp GR32:$src, (i32 0))),
(TZCNT32rr GR32:$src)>;
def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_NE),
(X86cmp GR64:$src, (i64 0))),
(TZCNT64rr GR64:$src)>;
def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
(X86cmp (loadi16 addr:$src), (i16 0))),
(TZCNT16rm addr:$src)>;
def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
(X86cmp (loadi32 addr:$src), (i32 0))),
(TZCNT32rm addr:$src)>;
def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
(X86cmp (loadi64 addr:$src), (i64 0))),
(TZCNT64rm addr:$src)>;
def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_NE),
(X86cmp (loadi16 addr:$src), (i16 0))),
(TZCNT16rm addr:$src)>;
def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_NE),
(X86cmp (loadi32 addr:$src), (i32 0))),
(TZCNT32rm addr:$src)>;
def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_NE),
(X86cmp (loadi64 addr:$src), (i64 0))),
(TZCNT64rm addr:$src)>;
}
multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
X86MemOperand x86memop, Intrinsic Int,