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[PowerPC] Use xxleqv to set all one vector IMM(-1).
Summary: xxspltib/vspltisb are 3 cycle PM instructions, xxleqv is 2 cycle ALU instruction. We should use xxleqv to set all one vectors. Reviewers: hfinkel, nemanjai, steven.zhang Subscribers: hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65529 llvm-svn: 369006
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@ -64,6 +64,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
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XXLAND,
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XXLANDC,
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XXLEQV,
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XXLEQVOnes,
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XXLNAND,
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XXLNOR,
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XXLOR,
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@ -335,6 +335,7 @@ bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
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case PPC::XXLXORz:
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case PPC::XXLXORspz:
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case PPC::XXLXORdpz:
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case PPC::XXLEQVOnes:
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case PPC::V_SET0B:
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case PPC::V_SET0H:
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case PPC::V_SET0:
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@ -386,7 +386,9 @@ def immZExt16 : PatLeaf<(imm), [{
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// field. Used by instructions like 'ori'.
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
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def immNonAllOneAnyExt8 : ImmLeaf<i32, [{
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return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF));
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}]>;
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def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
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// imm16Shifted* - These match immediates where the low 16-bits are zero. There
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@ -1310,6 +1310,13 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
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(XXLEQV $A, $B)>;
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let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
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isReMaterializable = 1 in {
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def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
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"xxleqv $XT, $XT, $XT", IIC_VecGeneral,
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[(set v4i32:$XT, (v4i32 immAllOnesV))]>;
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}
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def XXLORC : XX3Form<60, 170,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xxlorc $XT, $XA, $XB", IIC_VecGeneral,
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@ -4095,27 +4102,34 @@ let AddedComplexity = 400 in {
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(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
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}
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let Predicates = [HasP8Vector] in {
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def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
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(XXLEQVOnes)>;
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def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
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(v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
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def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
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(v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
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def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
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(v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
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def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
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(v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
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}
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let Predicates = [HasP9Vector] in {
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// Endianness-neutral patterns for const splats with ISA 3.0 instructions.
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def : Pat<(v4i32 (scalar_to_vector i32:$A)),
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(v4i32 (MTVSRWS $A))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
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(v4i32 (MTVSRWS $A))>;
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def : Pat<(v16i8 (build_vector immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
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immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
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immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
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immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
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immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
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immAnyExt8:$A)),
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def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
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immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
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def : Pat<(v16i8 immAllOnesV),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v8i16 immAllOnesV),
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(v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v4i32 immAllOnesV),
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(v4i32 (XXSPLTIB 255))>;
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def : Pat<(v2i64 immAllOnesV),
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(v2i64 (XXSPLTIB 255))>;
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def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
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(v4i32 (XVCVSPSXWS (LXVWSX xoaddr:$A)))>;
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def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
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@ -19,12 +19,12 @@ define <1 x i128> @One1i128() {
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;
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; P8LE-LABEL: One1i128:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vspltisb v2, -1
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One1i128:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxspltib vs34, 255
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <1 x i128> <i128 -1>
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@ -40,12 +40,12 @@ define <2 x i64> @One2i64() {
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;
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; P8LE-LABEL: One2i64:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vspltisb v2, -1
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One2i64:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxspltib vs34, 255
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <2 x i64> <i64 -1, i64 -1>
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@ -59,12 +59,12 @@ define <4 x i32> @One4i32() {
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;
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; P8LE-LABEL: One4i32:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vspltisb v2, -1
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One4i32:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxspltib vs34, 255
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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@ -78,12 +78,12 @@ define <8 x i16> @One8i16() {
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;
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; P8LE-LABEL: One8i16:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vspltisb v2, -1
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One8i16:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxspltib vs34, 255
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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@ -97,12 +97,12 @@ define <16 x i8> @One16i8() {
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;
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; P8LE-LABEL: One16i8:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vspltisb v2, -1
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One16i8:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxspltib vs34, 255
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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@ -217,12 +217,12 @@ entry:
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define <16 x i8> @test12() {
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; CHECK-LABEL: test12:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v2, 255
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; CHECK-NEXT: xxleqv v2, v2, v2
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test12:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxspltib v2, 255
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; CHECK-BE-NEXT: xxleqv v2, v2, v2
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; CHECK-BE-NEXT: blr
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entry:
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@ -396,12 +396,12 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: vaddubm 3, 2, 3
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; CHECK-NEXT: vcmpgtub 2, 2, 3
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; CHECK-NEXT: xxsel 34, 35, 36, 34
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; CHECK-NEXT: xxsel 34, 35, 0, 34
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; CHECK-NEXT: blr
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%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
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%c = icmp ugt <16 x i8> %x, %a
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@ -413,7 +413,7 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI26_1@toc@ha
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; CHECK-NEXT: vspltisb 5, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI26_1@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha
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@ -421,7 +421,7 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
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; CHECK-NEXT: vcmpgtub 3, 2, 3
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; CHECK-NEXT: lvx 4, 0, 3
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; CHECK-NEXT: vaddubm 2, 2, 4
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; CHECK-NEXT: xxsel 34, 34, 37, 35
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; CHECK-NEXT: xxsel 34, 34, 0, 35
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; CHECK-NEXT: blr
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%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
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%c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
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@ -451,12 +451,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: vadduhm 3, 2, 3
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; CHECK-NEXT: vcmpgtuh 2, 2, 3
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; CHECK-NEXT: xxsel 34, 35, 36, 34
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; CHECK-NEXT: xxsel 34, 35, 0, 34
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; CHECK-NEXT: blr
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%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
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%c = icmp ugt <8 x i16> %x, %a
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@ -468,7 +468,7 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI29_1@toc@ha
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; CHECK-NEXT: vspltisb 5, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI29_1@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha
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@ -476,7 +476,7 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
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; CHECK-NEXT: vcmpgtuh 3, 2, 3
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; CHECK-NEXT: lvx 4, 0, 3
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; CHECK-NEXT: vadduhm 2, 2, 4
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; CHECK-NEXT: xxsel 34, 34, 37, 35
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; CHECK-NEXT: xxsel 34, 34, 0, 35
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; CHECK-NEXT: blr
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%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
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%c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
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@ -506,12 +506,12 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: vadduwm 3, 2, 3
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; CHECK-NEXT: vcmpgtuw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 35, 36, 34
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; CHECK-NEXT: xxsel 34, 35, 0, 34
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; CHECK-NEXT: blr
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%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
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%c = icmp ugt <4 x i32> %x, %a
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@ -523,7 +523,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI32_1@toc@ha
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; CHECK-NEXT: vspltisb 5, -1
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: addi 3, 3, .LCPI32_1@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha
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@ -531,7 +531,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
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; CHECK-NEXT: vcmpgtuw 3, 2, 3
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; CHECK-NEXT: lvx 4, 0, 3
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; CHECK-NEXT: vadduwm 2, 2, 4
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; CHECK-NEXT: xxsel 34, 34, 37, 35
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; CHECK-NEXT: xxsel 34, 34, 0, 35
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; CHECK-NEXT: blr
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%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
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%c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
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@ -563,13 +563,13 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI34_0@toc@ha
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: addi 3, 3, .LCPI34_0@toc@l
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: xxleqv 0, 0, 0
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; CHECK-NEXT: vaddudm 3, 2, 3
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; CHECK-NEXT: vcmpgtud 2, 2, 3
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; CHECK-NEXT: xxsel 34, 35, 36, 34
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; CHECK-NEXT: xxsel 34, 35, 0, 34
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; CHECK-NEXT: blr
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%a = add <2 x i64> %x, <i64 42, i64 42>
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%c = icmp ugt <2 x i64> %x, %a
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@ -581,17 +581,17 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
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; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI35_1@toc@ha
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; CHECK-NEXT: vspltisb 5, -1
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; CHECK-NEXT: addi 3, 3, .LCPI35_1@toc@l
|
||||
; CHECK-NEXT: lxvd2x 0, 0, 3
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI35_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI35_0@toc@l
|
||||
; CHECK-NEXT: lxvd2x 1, 0, 3
|
||||
; CHECK-NEXT: xxswapd 35, 0
|
||||
; CHECK-NEXT: lxvd2x 0, 0, 3
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: xxswapd 36, 1
|
||||
; CHECK-NEXT: vcmpgtud 3, 2, 3
|
||||
; CHECK-NEXT: xxswapd 36, 0
|
||||
; CHECK-NEXT: vaddudm 2, 2, 4
|
||||
; CHECK-NEXT: xxsel 34, 34, 37, 35
|
||||
; CHECK-NEXT: xxsel 34, 34, 0, 35
|
||||
; CHECK-NEXT: blr
|
||||
%a = add <2 x i64> %x, <i64 42, i64 42>
|
||||
%c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
|
||||
@ -617,9 +617,9 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x
|
||||
; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vaddubm 3, 2, 3
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtub 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 35, 36, 34
|
||||
; CHECK-NEXT: xxsel 34, 35, 0, 34
|
||||
; CHECK-NEXT: blr
|
||||
%a = add <16 x i8> %x, %y
|
||||
%c = icmp ugt <16 x i8> %x, %a
|
||||
@ -631,10 +631,10 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16
|
||||
; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xxlnor 36, 35, 35
|
||||
; CHECK-NEXT: vspltisb 5, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtub 4, 2, 4
|
||||
; CHECK-NEXT: vaddubm 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 34, 37, 36
|
||||
; CHECK-NEXT: xxsel 34, 34, 0, 36
|
||||
; CHECK-NEXT: blr
|
||||
%noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
|
||||
%a = add <16 x i8> %x, %y
|
||||
@ -661,9 +661,9 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i
|
||||
; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vadduhm 3, 2, 3
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtuh 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 35, 36, 34
|
||||
; CHECK-NEXT: xxsel 34, 35, 0, 34
|
||||
; CHECK-NEXT: blr
|
||||
%a = add <8 x i16> %x, %y
|
||||
%c = icmp ugt <8 x i16> %x, %a
|
||||
@ -675,10 +675,10 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8
|
||||
; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xxlnor 36, 35, 35
|
||||
; CHECK-NEXT: vspltisb 5, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtuh 4, 2, 4
|
||||
; CHECK-NEXT: vadduhm 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 34, 37, 36
|
||||
; CHECK-NEXT: xxsel 34, 34, 0, 36
|
||||
; CHECK-NEXT: blr
|
||||
%noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
|
||||
%a = add <8 x i16> %x, %y
|
||||
@ -705,9 +705,9 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i
|
||||
; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vadduwm 3, 2, 3
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtuw 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 35, 36, 34
|
||||
; CHECK-NEXT: xxsel 34, 35, 0, 34
|
||||
; CHECK-NEXT: blr
|
||||
%a = add <4 x i32> %x, %y
|
||||
%c = icmp ugt <4 x i32> %x, %a
|
||||
@ -719,10 +719,10 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4
|
||||
; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xxlnor 36, 35, 35
|
||||
; CHECK-NEXT: vspltisb 5, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtuw 4, 2, 4
|
||||
; CHECK-NEXT: vadduwm 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 34, 37, 36
|
||||
; CHECK-NEXT: xxsel 34, 34, 0, 36
|
||||
; CHECK-NEXT: blr
|
||||
%noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%a = add <4 x i32> %x, %y
|
||||
@ -749,9 +749,9 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i
|
||||
; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vaddudm 3, 2, 3
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtud 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 35, 36, 34
|
||||
; CHECK-NEXT: xxsel 34, 35, 0, 34
|
||||
; CHECK-NEXT: blr
|
||||
%a = add <2 x i64> %x, %y
|
||||
%c = icmp ugt <2 x i64> %x, %a
|
||||
@ -763,10 +763,10 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
|
||||
; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xxlnor 36, 35, 35
|
||||
; CHECK-NEXT: vspltisb 5, -1
|
||||
; CHECK-NEXT: xxleqv 0, 0, 0
|
||||
; CHECK-NEXT: vcmpgtud 4, 2, 4
|
||||
; CHECK-NEXT: vaddudm 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 34, 37, 36
|
||||
; CHECK-NEXT: xxsel 34, 34, 0, 36
|
||||
; CHECK-NEXT: blr
|
||||
%noty = xor <2 x i64> %y, <i64 -1, i64 -1>
|
||||
%a = add <2 x i64> %x, %y
|
||||
|
@ -325,7 +325,7 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
; CHECK-LABEL: all_sign_bits_clear_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 36, 36, 36
|
||||
; CHECK-NEXT: xxlor 34, 34, 35
|
||||
; CHECK-NEXT: vcmpgtsw 2, 2, 4
|
||||
; CHECK-NEXT: blr
|
||||
@ -338,7 +338,7 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
; CHECK-LABEL: all_bits_set_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 36, 36, 36
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 4
|
||||
; CHECK-NEXT: blr
|
||||
@ -391,7 +391,7 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
; CHECK-LABEL: any_bits_clear_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 36, 36, 36
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 4
|
||||
; CHECK-NEXT: xxlnor 34, 34, 34
|
||||
@ -405,7 +405,7 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
|
||||
; CHECK-LABEL: any_sign_bits_clear_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxleqv 36, 36, 36
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: vcmpgtsw 2, 2, 4
|
||||
; CHECK-NEXT: blr
|
||||
|
@ -29,7 +29,7 @@ define i32 @add_zext_ifpos(i32 %x) {
|
||||
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
|
||||
; CHECK-LABEL: add_zext_ifpos_vec_splat:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 3, -1
|
||||
; CHECK-NEXT: xxleqv 35, 35, 35
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
|
||||
; CHECK-NEXT: vcmpgtsw 2, 2, 3
|
||||
@ -81,7 +81,7 @@ define i32 @add_sext_ifpos(i32 %x) {
|
||||
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
|
||||
; CHECK-LABEL: add_sext_ifpos_vec_splat:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisb 3, -1
|
||||
; CHECK-NEXT: xxleqv 35, 35, 35
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l
|
||||
; CHECK-NEXT: vcmpgtsw 2, 2, 3
|
||||
|
@ -80,7 +80,7 @@ define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {
|
||||
define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
|
||||
; VSX-LABEL: decrement_by_one:
|
||||
; VSX: # %bb.0:
|
||||
; VSX-NEXT: vspltisb 3, -1
|
||||
; VSX-NEXT: xxleqv 35, 35, 35
|
||||
; VSX-NEXT: vsubudm 2, 2, 3
|
||||
; VSX-NEXT: blr
|
||||
;
|
||||
|
@ -130,9 +130,9 @@ define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
|
||||
; CHECK-LABEL: sel_0_or_minus1_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vspltisw 3, 1
|
||||
; CHECK-NEXT: vspltisb 4, -1
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: vadduwm 2, 2, 4
|
||||
; CHECK-NEXT: xxleqv 35, 35, 35
|
||||
; CHECK-NEXT: vadduwm 2, 2, 3
|
||||
; CHECK-NEXT: blr
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
ret <4 x i32> %add
|
||||
|
Loading…
x
Reference in New Issue
Block a user