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[PowerPC] Disable direct moves for extractelement and bitcast in 32-bit mode

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This patch corresponds to review:
http://reviews.llvm.org/D17711

It disables direct moves on these operations in 32-bit mode since the patterns
assume 64-bit registers. The final patch is slightly different from the
Phabricator review as the bitcast operations needed to be disabled in 32-bit
mode as well. This fixes PR26617.

llvm-svn: 264282
This commit is contained in:
Nemanja Ivanovic 2016-03-24 13:40:33 +00:00
parent ae21770a8b
commit 7d010d19df
2 changed files with 17 additions and 2 deletions
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4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -255,7 +255,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
if (Subtarget.hasDirectMove()) {
if (Subtarget.hasDirectMove() && isPPC64) {
setOperationAction(ISD::BITCAST, MVT::f32, Legal);
setOperationAction(ISD::BITCAST, MVT::i32, Legal);
setOperationAction(ISD::BITCAST, MVT::i64, Legal);
@ -557,7 +557,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
}
if (Subtarget.hasDirectMove()) {
if (Subtarget.hasDirectMove() && isPPC64) {
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);

15
test/CodeGen/PowerPC/pr26617.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
define i32 @test(<4 x i32> %v, i32 %elem) #0 {
entry:
%vecext = extractelement <4 x i32> %v, i32 %elem
ret i32 %vecext
}
; CHECK: stxvw4x 34,
; CHECK: lwzx 3,
define float @test2(i32 signext %a) {
entry:
%conv = bitcast i32 %a to float
ret float %conv
}
; CHECK-NOT: mtvsr