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[RISCV] Support Shadow Call Stack
Currenlty assume x18 is used as pointer to shadow call stack. User shall pass flags: "-fsanitize=shadow-call-stack -ffixed-x18" Runtime supported is needed to setup x18. If SCS is desired, all parts of the program should be built with -ffixed-x18 to maintain inter-operatability. There's no particuluar reason that we must use x18 as SCS pointer. Any register may be used, as long as it does not have designated purpose already, like RA or passing call arguments. Differential Revision: https://reviews.llvm.org/D84414
This commit is contained in:
Zhaoshi Zheng
parent
f9eea5b8c6
commit
7d4e6e8ff5
@ -23,6 +23,105 @@
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using namespace llvm;
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// For now we use x18, a.k.a s2, as pointer to shadow call stack.
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// User should explicitly set -ffixed-x18 and not use x18 in their asm.
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static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const DebugLoc &DL) {
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if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
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return;
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const auto &STI = MF.getSubtarget<RISCVSubtarget>();
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Register RAReg = STI.getRegisterInfo()->getRARegister();
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// Do not save RA to the SCS if it's not saved to the regular stack,
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// i.e. RA is not at risk of being overwritten.
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std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
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if (std::none_of(CSI.begin(), CSI.end(),
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[&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
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return;
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Register SCSPReg = RISCVABI::getSCSPReg();
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auto &Ctx = MF.getFunction().getContext();
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if (!STI.isRegisterReservedByUser(SCSPReg)) {
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Ctx.diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
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return;
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}
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const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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if (RVFI->useSaveRestoreLibCalls(MF)) {
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Ctx.diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(),
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"Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
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return;
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}
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const RISCVInstrInfo *TII = STI.getInstrInfo();
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bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
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int64_t SlotSize = STI.getXLen() / 8;
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// Store return address to shadow call stack
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// s[w|d] ra, 0(s2)
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// addi s2, s2, [4|8]
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BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
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.addReg(RAReg)
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.addReg(SCSPReg)
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.addImm(0);
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BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
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.addReg(SCSPReg, RegState::Define)
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.addReg(SCSPReg)
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.addImm(SlotSize);
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}
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static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const DebugLoc &DL) {
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if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
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return;
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const auto &STI = MF.getSubtarget<RISCVSubtarget>();
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Register RAReg = STI.getRegisterInfo()->getRARegister();
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// See emitSCSPrologue() above.
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std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
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if (std::none_of(CSI.begin(), CSI.end(),
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[&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
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return;
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Register SCSPReg = RISCVABI::getSCSPReg();
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auto &Ctx = MF.getFunction().getContext();
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if (!STI.isRegisterReservedByUser(SCSPReg)) {
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Ctx.diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
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return;
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}
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const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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if (RVFI->useSaveRestoreLibCalls(MF)) {
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Ctx.diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(),
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"Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
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return;
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}
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const RISCVInstrInfo *TII = STI.getInstrInfo();
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bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
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int64_t SlotSize = STI.getXLen() / 8;
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// Load return address from shadow call stack
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// l[w|d] ra, -[4|8](s2)
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// addi s2, s2, -[4|8]
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BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
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.addReg(RAReg, RegState::Define)
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.addReg(SCSPReg)
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.addImm(-SlotSize);
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BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
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.addReg(SCSPReg, RegState::Define)
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.addReg(SCSPReg)
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.addImm(-SlotSize);
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}
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// Get the ID of the libcall used for spilling and restoring callee saved
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// registers. The ID is representative of the number of registers saved or
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// restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
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@ -222,15 +321,18 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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Register SPReg = getSPReg(STI);
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Register BPReg = RISCVABI::getBPReg();
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc DL;
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// Emit prologue for shadow call stack.
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emitSCSPrologue(MF, MBB, MBBI, DL);
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// Since spillCalleeSavedRegisters may have inserted a libcall, skip past
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// any instructions marked as FrameSetup
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while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
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++MBBI;
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc DL;
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// Determine the correct frame layout
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determineFrameLayout(MF);
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@ -457,6 +559,9 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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// Deallocate stack
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adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
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// Emit epilogue for shadow call stack.
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emitSCSEpilogue(MF, MBB, MBBI, DL);
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}
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int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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@ -67,6 +67,9 @@ ABI getTargetABI(StringRef ABIName) {
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// saved registers and X8 will be used as fp. So we choose X9 as bp.
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Register getBPReg() { return RISCV::X9; }
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// Returns the register holding shadow call stack pointer.
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Register getSCSPReg() { return RISCV::X18; }
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} // namespace RISCVABI
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namespace RISCVFeatures {
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@ -208,6 +208,9 @@ ABI getTargetABI(StringRef ABIName);
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// Returns the register used to hold the stack pointer after realignment.
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Register getBPReg();
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// Returns the register holding shadow call stack pointer.
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Register getSCSPReg();
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} // namespace RISCVABI
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namespace RISCVFeatures {
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174
test/CodeGen/RISCV/shadowcallstack.ll
Normal file
174
test/CodeGen/RISCV/shadowcallstack.ll
Normal file
@ -0,0 +1,174 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64
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define void @f1() shadowcallstack {
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; RV32-LABEL: f1:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f1:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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ret void
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}
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declare void @foo()
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define void @f2() shadowcallstack {
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; RV32-LABEL: f2:
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; RV32: # %bb.0:
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; RV32-NEXT: tail foo
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;
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; RV64-LABEL: f2:
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; RV64: # %bb.0:
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; RV64-NEXT: tail foo
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tail call void @foo()
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ret void
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}
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declare i32 @bar()
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define i32 @f3() shadowcallstack {
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; RV32-LABEL: f3:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: call bar
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f3:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: call bar
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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define i32 @f4() shadowcallstack {
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; RV32-LABEL: f4:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: sw s0, 8(sp)
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; RV32-NEXT: sw s1, 4(sp)
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; RV32-NEXT: sw s3, 0(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: .cfi_offset s1, -12
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; RV32-NEXT: .cfi_offset s3, -16
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s3, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s1, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s0, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: add a1, s3, s1
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; RV32-NEXT: add a0, s0, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lw s3, 0(sp)
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; RV32-NEXT: lw s1, 4(sp)
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; RV32-NEXT: lw s0, 8(sp)
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f4:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -32
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; RV64-NEXT: .cfi_def_cfa_offset 32
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; RV64-NEXT: sd ra, 24(sp)
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; RV64-NEXT: sd s0, 16(sp)
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; RV64-NEXT: sd s1, 8(sp)
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; RV64-NEXT: sd s3, 0(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: .cfi_offset s1, -24
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; RV64-NEXT: .cfi_offset s3, -32
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s3, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s1, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s0, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: add a1, s3, s1
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; RV64-NEXT: add a0, s0, a0
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; RV64-NEXT: addw a0, a1, a0
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; RV64-NEXT: ld s3, 0(sp)
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; RV64-NEXT: ld s1, 8(sp)
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; RV64-NEXT: ld s0, 16(sp)
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; RV64-NEXT: ld ra, 24(sp)
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; RV64-NEXT: addi sp, sp, 32
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res1 = call i32 @bar()
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%res2 = call i32 @bar()
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%res3 = call i32 @bar()
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%res4 = call i32 @bar()
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%res12 = add i32 %res1, %res2
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%res34 = add i32 %res3, %res4
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%res1234 = add i32 %res12, %res34
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ret i32 %res1234
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}
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define i32 @f5() shadowcallstack nounwind {
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; RV32-LABEL: f5:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: call bar
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f5:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: call bar
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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