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Default ISD::PREFETCH to expand.
llvm-svn: 48169
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parent
067ecbc341
commit
7d9e5a7680
@ -179,6 +179,9 @@ TargetLowering::TargetLowering(TargetMachine &tm)
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setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
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}
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// Most targets ignore the @llvm.prefetch intrinsic.
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// ConstantFP nodes default to expand. Targets can either change this to
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// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
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// to optimize expansions for certain constants.
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@ -211,7 +211,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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if (!Subtarget->hasV6Ops()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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@ -116,7 +116,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool and
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// ExternalSymbols nodes into the appropriate instructions to
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@ -321,7 +321,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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// Cell SPU has instructions for converting between i64 and fp.
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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@ -109,7 +109,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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// Thread Local Storage
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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@ -84,7 +84,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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@ -82,7 +82,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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@ -197,7 +197,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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@ -286,8 +286,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MEMSET , MVT::Other, Custom);
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setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
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if (!Subtarget->hasSSE1())
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setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
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if (Subtarget->hasSSE1())
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setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
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if (!Subtarget->hasSSE2())
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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