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[WebAssembly] Fix incorrect assumption of simple value types

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Fixes PR47375, in which an assertion was triggering because
WebAssemblyTargetLowering::isVectorLoadExtDesirable was improperly
assuming the use of simple value types.

Differential Revision: https://reviews.llvm.org/D87110

(cherry picked from commit caee15a0ed52471bd329d01dc253ec9be3936c6d)
This commit is contained in:
Thomas Lively 2020-09-06 15:42:21 -07:00 committed by Hans Wennborg
parent 0abe177619
commit 7da9b1dbc7
2 changed files with 38 additions and 2 deletions
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4
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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@ -601,8 +601,8 @@ bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT,
}
bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
MVT ExtT = ExtVal.getSimpleValueType();
MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
EVT ExtT = ExtVal.getValueType();
EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0);
return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
(ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
(ExtT == MVT::v2i64 && MemT == MVT::v2i32);

36
test/CodeGen/WebAssembly/pr47375.ll Normal file
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@ -0,0 +1,36 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
; Regression test for pr47375, in which an assertion was triggering
; because WebAssemblyTargetLowering::isVectorLoadExtDesirable was
; improperly assuming the use of simple value types.
define void @sext_vec() {
; CHECK-LABEL: sext_vec:
; CHECK: .functype sext_vec () -> ()
; CHECK-NEXT: .local i32
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.load8_u 0
; CHECK-NEXT: local.set 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 0
; CHECK-NEXT: i32.store8 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 7
; CHECK-NEXT: i32.shl
; CHECK-NEXT: i32.or
; CHECK-NEXT: i32.const 7175
; CHECK-NEXT: i32.and
; CHECK-NEXT: i32.store16 0
; CHECK-NEXT: # fallthrough-return
%L1 = load <2 x i3>, <2 x i3>* undef, align 2
%zext = zext <2 x i3> %L1 to <2 x i10>
store <2 x i10> %zext, <2 x i10>* undef, align 4
ret void
}