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fix a bunch of 80-col violations

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llvm-svn: 55588
This commit is contained in:
Gabor Greif 2008-08-31 15:37:04 +00:00
parent 297eb080b6
commit 7db742d8c2
5 changed files with 65 additions and 33 deletions
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42
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -414,7 +414,8 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB"; node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
node_names[(unsigned) SPUISD::PROMOTE_SCALAR] = "SPUISD::PROMOTE_SCALAR"; node_names[(unsigned) SPUISD::PROMOTE_SCALAR] = "SPUISD::PROMOTE_SCALAR";
node_names[(unsigned) SPUISD::EXTRACT_ELT0] = "SPUISD::EXTRACT_ELT0"; node_names[(unsigned) SPUISD::EXTRACT_ELT0] = "SPUISD::EXTRACT_ELT0";
node_names[(unsigned) SPUISD::EXTRACT_ELT0_CHAINED] = "SPUISD::EXTRACT_ELT0_CHAINED"; node_names[(unsigned) SPUISD::EXTRACT_ELT0_CHAINED]
= "SPUISD::EXTRACT_ELT0_CHAINED";
node_names[(unsigned) SPUISD::EXTRACT_I1_ZEXT] = "SPUISD::EXTRACT_I1_ZEXT"; node_names[(unsigned) SPUISD::EXTRACT_I1_ZEXT] = "SPUISD::EXTRACT_I1_ZEXT";
node_names[(unsigned) SPUISD::EXTRACT_I1_SEXT] = "SPUISD::EXTRACT_I1_SEXT"; node_names[(unsigned) SPUISD::EXTRACT_I1_SEXT] = "SPUISD::EXTRACT_I1_SEXT";
node_names[(unsigned) SPUISD::EXTRACT_I8_ZEXT] = "SPUISD::EXTRACT_I8_ZEXT"; node_names[(unsigned) SPUISD::EXTRACT_I8_ZEXT] = "SPUISD::EXTRACT_I8_ZEXT";
@ -509,7 +510,8 @@ AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
if (basePtr.getOpcode() == ISD::ADD) { if (basePtr.getOpcode() == ISD::ADD) {
SDValue Op1 = basePtr.getNode()->getOperand(1); SDValue Op1 = basePtr.getNode()->getOperand(1);
if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) { if (Op1.getOpcode() == ISD::Constant
|| Op1.getOpcode() == ISD::TargetConstant) {
const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1)); const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
alignOffs = (int) CN->getValue(); alignOffs = (int) CN->getValue();
@ -561,7 +563,8 @@ AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
// Unaligned load or we're using the "large memory" model, which means that // Unaligned load or we're using the "large memory" model, which means that
// we have to be very pessimistic: // we have to be very pessimistic:
if (isMemoryOperand(basePtr) || isIndirectOperand(basePtr)) { if (isMemoryOperand(basePtr) || isIndirectOperand(basePtr)) {
basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, basePtr,
DAG.getConstant(0, PtrVT));
} }
// Add the offset // Add the offset
@ -801,7 +804,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
} }
assert(0 && assert(0 &&
"LowerConstantPool: Relocation model other than static not supported."); "LowerConstantPool: Relocation model other than static"
" not supported.");
return SDValue(); return SDValue();
} }
@ -936,7 +940,8 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Add DAG nodes to load the arguments or copy them out of registers. // Add DAG nodes to load the arguments or copy them out of registers.
for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) { for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
ArgNo != e; ++ArgNo) {
SDValue ArgVal; SDValue ArgVal;
bool needsLoad = false; bool needsLoad = false;
MVT ObjectVT = Op.getValue(ArgNo).getValueType(); MVT ObjectVT = Op.getValue(ArgNo).getValueType();
@ -1556,7 +1561,8 @@ static bool isConstantSplat(const uint64_t Bits128[2],
if (MinSplatBits < 16) { if (MinSplatBits < 16) {
// If the top 8-bits are different than the lower 8-bits, ignoring // If the top 8-bits are different than the lower 8-bits, ignoring
// undefs, we have an i16 splat. // undefs, we have an i16 splat.
if ((Bits16 & (uint16_t(~Undef16) >> 8)) == ((Bits16 >> 8) & ~Undef16)) { if ((Bits16 & (uint16_t(~Undef16) >> 8))
== ((Bits16 >> 8) & ~Undef16)) {
// Otherwise, we have an 8-bit splat. // Otherwise, we have an 8-bit splat.
SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
@ -1820,7 +1826,8 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
// Use shuffle mask in SHUFB synthetic instruction: // Use shuffle mask in SHUFB synthetic instruction:
return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp); return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp);
} else { } else {
// Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes. // Convert the SHUFFLE_VECTOR mask's input element units to the
// actual bytes.
unsigned BytesPerElement = EltVT.getSizeInBits()/8; unsigned BytesPerElement = EltVT.getSizeInBits()/8;
SmallVector<SDValue, 16> ResultMask; SmallVector<SDValue, 16> ResultMask;
@ -2007,9 +2014,11 @@ static SDValue LowerVectorMUL(SDValue Op, SelectionDAG &DAG) {
SDValue HHProd_1 = SDValue HHProd_1 =
DAG.getNode(SPUISD::MPY, MVT::v8i16, DAG.getNode(SPUISD::MPY, MVT::v8i16,
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rAH, c8)), DAG.getNode(SPUISD::VEC_SRA,
MVT::v4i32, rAH, c8)),
DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rBH, c8))); DAG.getNode(SPUISD::VEC_SRA,
MVT::v4i32, rBH, c8)));
SDValue HHProd = SDValue HHProd =
DAG.getNode(SPUISD::SELB, MVT::v8i16, DAG.getNode(SPUISD::SELB, MVT::v8i16,
@ -2210,7 +2219,9 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1) ? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -2228,7 +2239,9 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1) ? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -2241,7 +2254,9 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
N0 = (N0.getOpcode() != ISD::Constant N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE; N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::SIGN_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1) ? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16)); : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
@ -3022,7 +3037,8 @@ SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
/// isLegalAddressImmediate - Return true if the integer value can be used /// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode. /// as the offset of the target addressing mode.
bool SPUTargetLowering::isLegalAddressImmediate(int64_t V, const Type *Ty) const { bool SPUTargetLowering::isLegalAddressImmediate(int64_t V,
const Type *Ty) const {
// SPU's addresses are 256K: // SPU's addresses are 256K:
return (V > -(1 << 18) && V < (1 << 18) - 1); return (V > -(1 << 18) && V < (1 << 18) - 1);
} }

6
lib/Target/CellSPU/SPUOperands.td
View File

@ -24,7 +24,8 @@ def LO16_vec : SDNodeXForm<scalar_to_vector, [{
&& "LO16_vec got something other than a BUILD_VECTOR"); && "LO16_vec got something other than a BUILD_VECTOR");
// Get first constant operand... // Get first constant operand...
for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) { for (unsigned i = 0, e = N->getNumOperands();
OpVal.getNode() == 0 && i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
if (OpVal.getNode() == 0) if (OpVal.getNode() == 0)
OpVal = N->getOperand(i); OpVal = N->getOperand(i);
@ -49,7 +50,8 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
&& "HI16_vec got something other than a BUILD_VECTOR"); && "HI16_vec got something other than a BUILD_VECTOR");
// Get first constant operand... // Get first constant operand...
for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) { for (unsigned i = 0, e = N->getNumOperands();
OpVal.getNode() == 0 && i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
if (OpVal.getNode() == 0) if (OpVal.getNode() == 0)
OpVal = N->getOperand(i); OpVal = N->getOperand(i);

6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -294,7 +294,8 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
} }
} }
return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).getNode(); return CurDAG->getRegister(GlobalBaseReg,
PPCLowering.getPointerTy()).getNode();
} }
/// isIntS16Immediate - This method tests to see if the node is either a 32-bit /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
@ -348,7 +349,8 @@ static bool isInt32Immediate(SDValue N, unsigned &Imm) {
// opcode and that it has a immediate integer right operand. // opcode and that it has a immediate integer right operand.
// If so Imm will receive the 32 bit value. // If so Imm will receive the 32 bit value.
static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).getNode(), Imm); return N->getOpcode() == Opc
&& isInt32Immediate(N->getOperand(1).getNode(), Imm);
} }
bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {

9
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1440,7 +1440,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
SmallVector<SDValue, 8> MemOps; SmallVector<SDValue, 8> MemOps;
unsigned nAltivecParamsAtEnd = 0; unsigned nAltivecParamsAtEnd = 0;
for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) { for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
ArgNo != e; ++ArgNo) {
SDValue ArgVal; SDValue ArgVal;
bool needsLoad = false; bool needsLoad = false;
MVT ObjectVT = Op.getValue(ArgNo).getValueType(); MVT ObjectVT = Op.getValue(ArgNo).getValueType();
@ -2199,7 +2200,8 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// This must go outside the CALLSEQ_START..END. // This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.getNode()->getOperand(1)); CallSeqStart.getNode()->getOperand(1));
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
NewCallSeqStart.getNode());
Chain = CallSeqStart = NewCallSeqStart; Chain = CallSeqStart = NewCallSeqStart;
ArgOffset += PtrByteSize; ArgOffset += PtrByteSize;
} }
@ -2461,7 +2463,8 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
// to do the call, we can't use PPCISD::CALL. // to do the call, we can't use PPCISD::CALL.
SDValue MTCTROps[] = {Chain, Callee, InFlag}; SDValue MTCTROps[] = {Chain, Callee, InFlag};
Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.getNode()!=0)); Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps,
2 + (InFlag.getNode() != 0));
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
// Copy the callee address into R12/X12 on darwin. // Copy the callee address into R12/X12 on darwin.

35
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -80,12 +80,14 @@ namespace {
} }
void dump() { void dump() {
cerr << "X86ISelAddressMode " << this << "\n"; cerr << "X86ISelAddressMode " << this << "\n";
cerr << "Base.Reg "; if (Base.Reg.getNode()!=0) Base.Reg.getNode()->dump(); cerr << "Base.Reg ";
else cerr << "nul"; if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
else cerr << "nul";
cerr << " Base.FrameIndex " << Base.FrameIndex << "\n"; cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n"; cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
cerr << "IndexReg "; if (IndexReg.getNode()!=0) IndexReg.getNode()->dump(); cerr << "IndexReg ";
else cerr << "nul"; if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
else cerr << "nul";
cerr << " Disp " << Disp << "\n"; cerr << " Disp " << Disp << "\n";
cerr << "GV "; if (GV) GV->dump(); cerr << "GV "; if (GV) GV->dump();
else cerr << "nul"; else cerr << "nul";
@ -202,7 +204,8 @@ namespace {
if (AM.GV) if (AM.GV)
Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp); Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
else if (AM.CP) else if (AM.CP)
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp); Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
AM.Align, AM.Disp);
else if (AM.ES) else if (AM.ES)
Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32); Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
else if (AM.JT != -1) else if (AM.JT != -1)
@ -245,7 +248,8 @@ namespace {
}; };
} }
/// findFlagUse - Return use of MVT::Flag value produced by the specified SDNode. /// findFlagUse - Return use of MVT::Flag value produced by the specified
/// SDNode.
/// ///
static SDNode *findFlagUse(SDNode *N) { static SDNode *findFlagUse(SDNode *N) {
unsigned FlagResNo = N->getNumValues()-1; unsigned FlagResNo = N->getNumValues()-1;
@ -847,7 +851,8 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
} }
case ISD::FrameIndex: case ISD::FrameIndex:
if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.getNode() == 0) { if (AM.BaseType == X86ISelAddressMode::RegBase
&& AM.Base.Reg.getNode() == 0) {
AM.BaseType = X86ISelAddressMode::FrameIndexBase; AM.BaseType = X86ISelAddressMode::FrameIndexBase;
AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
return false; return false;
@ -855,10 +860,12 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
break; break;
case ISD::SHL: case ISD::SHL:
if (AlreadySelected || AM.IndexReg.getNode() != 0 || AM.Scale != 1 || AM.isRIPRel) if (AlreadySelected || AM.IndexReg.getNode() != 0
|| AM.Scale != 1 || AM.isRIPRel)
break; break;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { if (ConstantSDNode
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
unsigned Val = CN->getValue(); unsigned Val = CN->getValue();
if (Val == 1 || Val == 2 || Val == 3) { if (Val == 1 || Val == 2 || Val == 3) {
AM.Scale = 1 << Val; AM.Scale = 1 << Val;
@ -897,7 +904,8 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
AM.Base.Reg.getNode() == 0 && AM.Base.Reg.getNode() == 0 &&
AM.IndexReg.getNode() == 0 && AM.IndexReg.getNode() == 0 &&
!AM.isRIPRel) { !AM.isRIPRel) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) if (ConstantSDNode
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) { if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
AM.Scale = unsigned(CN->getValue())-1; AM.Scale = unsigned(CN->getValue())-1;
@ -1298,7 +1306,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1), SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
CurDAG->getRegister(0, PtrVT), C }; CurDAG->getRegister(0, PtrVT), C };
return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r, MVT::i64, Ops, 4); return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r,
MVT::i64, Ops, 4);
} else } else
return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri, PtrVT, C); return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri, PtrVT, C);
} }
@ -1393,7 +1402,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
X86::AX, MVT::i16, InFlag); X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2); InFlag = Result.getValue(2);
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0); CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8. // Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
@ -1552,7 +1561,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
X86::AX, MVT::i16, InFlag); X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2); InFlag = Result.getValue(2);
Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result, Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0); CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8. // Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,