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[RISCV] Support machine constraint "S"

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Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

  extern int var;
  void *addr_via_asm() {
    void *ret;
    asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
    return ret;
  }

'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105254
This commit is contained in:
Fangrui Song 2021-07-13 09:30:09 -07:00
parent 79316cfa46
commit 7dbb7fdf61
2 changed files with 65 additions and 0 deletions
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11
lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -8294,6 +8294,8 @@ RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
return C_Immediate; return C_Immediate;
case 'A': case 'A':
return C_Memory; return C_Memory;
case 'S': // A symbolic address
return C_Other;
} }
} }
return TargetLowering::getConstraintType(Constraint); return TargetLowering::getConstraintType(Constraint);
@ -8523,6 +8525,15 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint(
DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT())); DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
} }
return; return;
case 'S':
if (const auto *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
GA->getValueType(0)));
} else if (const auto *BA = dyn_cast<BlockAddressSDNode>(Op)) {
Ops.push_back(DAG.getTargetBlockAddress(BA->getBlockAddress(),
BA->getValueType(0)));
}
return;
default: default:
break; break;
} }

54
test/CodeGen/RISCV/inline-asm-S-constraint.ll Normal file
View File

@ -0,0 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
@var = external dso_local global i32, align 4
define dso_local i8* @constraint_S() {
; RV32-LABEL: constraint_S:
; RV32: # %bb.0:
; RV32-NEXT: #APP
; RV32-NEXT: lui a0, %hi(var)
; RV32-NEXT: addi a0, a0, %lo(var)
; RV32-NEXT: #NO_APP
; RV32-NEXT: ret
;
; RV64-LABEL: constraint_S:
; RV64: # %bb.0:
; RV64-NEXT: #APP
; RV64-NEXT: lui a0, %hi(var)
; RV64-NEXT: addi a0, a0, %lo(var)
; RV64-NEXT: #NO_APP
; RV64-NEXT: ret
%ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i32* nonnull @var)
ret i8* %ret
}
; Function Attrs: nofree nosync nounwind readnone
define dso_local i8* @constraint_S_label() {
; RV32-LABEL: constraint_S_label:
; RV32: # %bb.0: # %entry
; RV32-NEXT: .Ltmp0: # Block address taken
; RV32-NEXT: # %bb.1: # %L1
; RV32-NEXT: #APP
; RV32-NEXT: lui a0, %hi(.Ltmp0)
; RV32-NEXT: addi a0, a0, %lo(.Ltmp0)
; RV32-NEXT: #NO_APP
; RV32-NEXT: ret
;
; RV64-LABEL: constraint_S_label:
; RV64: # %bb.0: # %entry
; RV64-NEXT: .Ltmp0: # Block address taken
; RV64-NEXT: # %bb.1: # %L1
; RV64-NEXT: #APP
; RV64-NEXT: lui a0, %hi(.Ltmp0)
; RV64-NEXT: addi a0, a0, %lo(.Ltmp0)
; RV64-NEXT: #NO_APP
; RV64-NEXT: ret
entry:
br label %L1
L1:
%ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i8* blockaddress(@constraint_S_label, %L1))
ret i8* %ret
}