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Fix some load/store logic that would be wrong for
apints on big-endian machines if the bitwidth is not a multiple of 8. Introduce a new helper, MVT::getStoreSizeInBits, and use it. llvm-svn: 43934
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@ -243,6 +243,13 @@ namespace MVT { // MVT = Machine Value Types
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}
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}
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}
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}
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/// MVT::getStoreSizeInBits - Return the number of bits overwritten by a
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/// store of the specified value type.
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///
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static inline unsigned getStoreSizeInBits(ValueType VT) {
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return (getSizeInBits(VT) + 7)/8*8;
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}
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/// MVT::getIntegerType - Returns the ValueType that represents an integer
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/// MVT::getIntegerType - Returns the ValueType that represents an integer
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/// with the given number of bits.
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/// with the given number of bits.
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///
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///
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@ -1713,8 +1713,9 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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// For big endian targets, we need to add an offset to the pointer to
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// For big endian targets, we need to add an offset to the pointer to
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// load the correct bytes. For little endian systems, we merely need to
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// load the correct bytes. For little endian systems, we merely need to
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// read fewer bytes from the same pointer.
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// read fewer bytes from the same pointer.
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unsigned PtrOff =
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unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
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(MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
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unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
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unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
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unsigned Alignment = LN0->getAlignment();
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unsigned Alignment = LN0->getAlignment();
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SDOperand NewPtr = LN0->getBasePtr();
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SDOperand NewPtr = LN0->getBasePtr();
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if (!TLI.isLittleEndian()) {
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if (!TLI.isLittleEndian()) {
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@ -2991,8 +2992,11 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
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MVT::ValueType PtrType = N0.getOperand(1).getValueType();
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MVT::ValueType PtrType = N0.getOperand(1).getValueType();
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// For big endian targets, we need to adjust the offset to the pointer to
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// For big endian targets, we need to adjust the offset to the pointer to
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// load the correct bytes.
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// load the correct bytes.
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if (!TLI.isLittleEndian())
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if (!TLI.isLittleEndian()) {
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ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
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unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
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unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
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ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
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}
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uint64_t PtrOff = ShAmt / 8;
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uint64_t PtrOff = ShAmt / 8;
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unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
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unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
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SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
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SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
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@ -1036,7 +1036,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
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// Big-endian - high bits are at low addresses. Favor aligned loads at
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// Big-endian - high bits are at low addresses. Favor aligned loads at
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// the cost of some bit-fiddling.
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// the cost of some bit-fiddling.
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MVT::ValueType EVT = N->getLoadedVT();
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MVT::ValueType EVT = N->getLoadedVT();
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unsigned EBytes = (MVT::getSizeInBits(EVT) + 7)/8;
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unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
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unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
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unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
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unsigned ExcessBits = (EBytes - IncrementSize)*8;
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unsigned ExcessBits = (EBytes - IncrementSize)*8;
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@ -2069,7 +2069,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
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GetExpandedOp(N->getValue(), Lo, Hi);
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GetExpandedOp(N->getValue(), Lo, Hi);
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MVT::ValueType EVT = N->getStoredVT();
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MVT::ValueType EVT = N->getStoredVT();
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unsigned EBytes = (MVT::getSizeInBits(EVT) + 7)/8;
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unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
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unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
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unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
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unsigned ExcessBits = (EBytes - IncrementSize)*8;
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unsigned ExcessBits = (EBytes - IncrementSize)*8;
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MVT::ValueType HiVT =
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MVT::ValueType HiVT =
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