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[AArch64][GlobalISel] Properly implement widening for TB(N)Z
When we have to widen to a 64-bit register, we have to emit a SUBREG_TO_REG. Add a general-purpose widening helpe which emits the correct SUBREG_TO_REG instruction based off of a desired size and add a testcase. Also remove some asserts which are technically incorrect in `emitTestBit`. - p0 doesn't count as a scalar type, so we need to check `!Ty.isVector()` instead - Whenever we have a s1, the Size/Bit checks are too conservative, so just remove them Replace these asserts with less conservative ones where applicable. Differential Revision: https://reviews.llvm.org/D74427
This commit is contained in:
Jessica Paquette
parent
ed8bd8f4b1
commit
7e17214e5b
@ -273,6 +273,8 @@ private:
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/// new copy.
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Register narrowExtendRegIfNeeded(Register ExtReg,
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MachineIRBuilder &MIB) const;
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Register widenGPRBankRegIfNeeded(Register Reg, unsigned Size,
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MachineIRBuilder &MIB) const;
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ComplexRendererFns selectArithExtendedRegister(MachineOperand &Root) const;
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void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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@ -1124,26 +1126,25 @@ static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
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MachineInstr *AArch64InstructionSelector::emitTestBit(
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Register TestReg, uint64_t Bit, bool IsNegative, MachineBasicBlock *DstMBB,
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MachineIRBuilder &MIB) const {
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MachineRegisterInfo &MRI = *MIB.getMRI();
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#ifndef NDEBUG
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assert(TestReg.isValid());
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assert(ProduceNonFlagSettingCondBr &&
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"Cannot emit TB(N)Z with speculation tracking!");
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assert(TestReg.isValid());
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LLT Ty = MRI.getType(TestReg);
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unsigned Size = Ty.getSizeInBits();
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assert(Bit < Size &&
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"Bit to test must be smaler than the size of a test register!");
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assert(Ty.isScalar() && "Expected a scalar!");
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assert(Size >= 32 && "Expected at least a 32-bit register!");
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#endif
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MachineRegisterInfo &MRI = *MIB.getMRI();
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// Attempt to optimize the test bit by walking over instructions.
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TestReg = getTestBitReg(TestReg, Bit, IsNegative, MRI);
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bool UseWReg = Bit < 32;
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LLT Ty = MRI.getType(TestReg);
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unsigned Size = Ty.getSizeInBits();
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assert(!Ty.isVector() && "Expected a scalar!");
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assert(Bit < 64 && "Bit is too large!");
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// When the test register is a 64-bit register, we have to narrow to make
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// TBNZW work.
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if (UseWReg)
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bool UseWReg = Bit < 32;
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unsigned NecessarySize = UseWReg ? 32 : 64;
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if (Size < NecessarySize)
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TestReg = widenGPRBankRegIfNeeded(TestReg, NecessarySize, MIB);
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else if (Size > NecessarySize)
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TestReg = narrowExtendRegIfNeeded(TestReg, MIB);
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static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX},
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@ -5154,6 +5155,52 @@ Register AArch64InstructionSelector::narrowExtendRegIfNeeded(
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return Copy.getReg(0);
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}
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Register AArch64InstructionSelector::widenGPRBankRegIfNeeded(
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Register Reg, unsigned WideSize, MachineIRBuilder &MIB) const {
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assert(WideSize >= 8 && "WideSize is smaller than all possible registers?");
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MachineRegisterInfo &MRI = *MIB.getMRI();
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unsigned NarrowSize = MRI.getType(Reg).getSizeInBits();
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assert(WideSize >= NarrowSize &&
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"WideSize cannot be smaller than NarrowSize!");
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// If the sizes match, just return the register.
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//
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// If NarrowSize is an s1, then we can select it to any size, so we'll treat
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// it as a don't care.
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if (NarrowSize == WideSize || NarrowSize == 1)
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return Reg;
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// Now check the register classes.
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const RegisterBank *RB = RBI.getRegBank(Reg, MRI, TRI);
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const TargetRegisterClass *OrigRC = getMinClassForRegBank(*RB, NarrowSize);
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const TargetRegisterClass *WideRC = getMinClassForRegBank(*RB, WideSize);
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assert(OrigRC && "Could not determine narrow RC?");
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assert(WideRC && "Could not determine wide RC?");
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// If the sizes differ, but the register classes are the same, there is no
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// need to insert a SUBREG_TO_REG.
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//
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// For example, an s8 that's supposed to be a GPR will be selected to either
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// a GPR32 or a GPR64 register. Note that this assumes that the s8 will
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// always end up on a GPR32.
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if (OrigRC == WideRC)
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return Reg;
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// We have two different register classes. Insert a SUBREG_TO_REG.
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unsigned SubReg = 0;
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getSubRegForClass(OrigRC, TRI, SubReg);
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assert(SubReg && "Couldn't determine subregister?");
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// Build the SUBREG_TO_REG and return the new, widened register.
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auto SubRegToReg =
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MIB.buildInstr(AArch64::SUBREG_TO_REG, {WideRC}, {})
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.addImm(0)
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.addUse(Reg)
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.addImm(SubReg);
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constrainSelectedInstRegOperands(*SubRegToReg, TII, TRI, RBI);
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return SubRegToReg.getReg(0);
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}
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/// Select an "extended register" operand. This operand folds in an extend
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/// followed by an optional left shift.
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InstructionSelector::ComplexRendererFns
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@ -78,9 +78,8 @@ body: |
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $h0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
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; CHECK: %copy:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy
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; CHECK: TBNZW [[COPY]], 3, %bb.1
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; CHECK: %copy:gpr32 = COPY [[SUBREG_TO_REG]]
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; CHECK: TBNZW %copy, 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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193
test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
Normal file
193
test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
Normal file
@ -0,0 +1,193 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test widening and narrowing on test bit operations using subregister copies
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# or SUBREG_TO_REG.
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--- |
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@glob = external unnamed_addr global i1, align 4
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define void @s1_no_copy() { ret void }
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define void @s16_no_copy() { ret void }
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define void @p0_no_copy() { ret void }
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define void @widen_s32_to_s64() { ret void }
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define void @widen_s16_to_s64() { ret void }
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define void @narrow_s64_to_s32() { ret void }
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...
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---
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name: s1_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: s1_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %narrow:gpr32 = IMPLICIT_DEF
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; CHECK: TBNZW %narrow, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%narrow:gpr(s1) = G_IMPLICIT_DEF
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; There should be no copy here, because the s1 can be selected to a GPR32.
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G_BRCOND %narrow(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: s16_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: s16_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %narrow:gpr32 = IMPLICIT_DEF
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; CHECK: TBNZW %narrow, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%narrow:gpr(s16) = G_IMPLICIT_DEF
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%trunc:gpr(s1) = G_TRUNC %narrow(s16)
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; Look through the G_TRUNC to get the G_IMPLICIT_DEF. We don't need a
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; SUBREG_TO_REG here, because the s16 will end up on a 32-bit register.
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: p0_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: p0_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
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; CHECK: %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load 1 from @glob, align 4)
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; CHECK: TBNZW %load, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%glob:gpr(p0) = G_GLOBAL_VALUE @glob
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%load:gpr(s8) = G_LOAD %glob(p0) :: (dereferenceable load 1 from @glob, align 4)
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%trunc:gpr(s1) = G_TRUNC %load(s8)
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; Look through G_TRUNC to get the load. The load is into a s8, which will
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; be selected to a GPR32, so we don't need a copy.
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: widen_s32_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: widen_s32_to_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $w0
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; CHECK: %reg:gpr32all = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32
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; CHECK: TBZX [[SUBREG_TO_REG]], 33, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%reg:gpr(s32) = COPY $w0
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%zext:gpr(s64) = G_ZEXT %reg(s32)
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%bit:gpr(s64) = G_CONSTANT i64 8589934592
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%zero:gpr(s64) = G_CONSTANT i64 0
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%and:gpr(s64) = G_AND %zext, %bit
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%cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
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; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
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; bit 33. The subregister should be sub_32.
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%trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: widen_s16_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: widen_s16_to_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %reg:gpr32 = IMPLICIT_DEF
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32
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; CHECK: TBZX [[SUBREG_TO_REG]], 33, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%reg:gpr(s16) = G_IMPLICIT_DEF
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%zext:gpr(s64) = G_ZEXT %reg(s16)
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%bit:gpr(s64) = G_CONSTANT i64 8589934592
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%zero:gpr(s64) = G_CONSTANT i64 0
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%and:gpr(s64) = G_AND %zext, %bit
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%cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
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; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
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; bit 33. The subregister should be sub_32, because s16 will end up on a
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; GPR32.
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%trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: narrow_s64_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: narrow_s64_to_s32
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %wide:gpr64 = COPY $x0
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; CHECK: %trunc:gpr32 = COPY %wide.sub_32
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; CHECK: TBNZW %trunc, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%wide:gpr(s64) = COPY $x0
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; We should narrow using a subregister copy here.
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%trunc:gpr(s1) = G_TRUNC %wide(s64)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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