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https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 13:11:39 +01:00
[MIPS GlobalISel] Select MSA vector generic and builtin mul
Select vector G_MUL for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. Manual selection of G_MUL is now done for gprb only. __builtin_msa_mulv_<format> will be transformed into G_MUL in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69310
This commit is contained in:
Petar Avramovic
parent
dfd40f4f0d
commit
7e4c1ab813
@ -239,7 +239,9 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
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return true;
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}
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if (I.getOpcode() == Mips::G_MUL) {
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if (I.getOpcode() == Mips::G_MUL &&
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(RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
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Mips::GPRBRegBankID)) {
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MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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@ -61,11 +61,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder(G_MUL)
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_ADD, G_SUB})
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTyN(0, Query, {s32}))
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return true;
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@ -377,6 +373,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
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case Intrinsic::mips_subvi_d:
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return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
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case Intrinsic::mips_mulv_b:
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case Intrinsic::mips_mulv_h:
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case Intrinsic::mips_mulv_w:
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case Intrinsic::mips_mulv_d:
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return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
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default:
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break;
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}
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@ -437,7 +437,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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switch (Opc) {
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case G_TRUNC:
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case G_MUL:
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case G_UMULH:
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case G_ZEXTLOAD:
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case G_SEXTLOAD:
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@ -460,6 +459,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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break;
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case G_ADD:
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case G_SUB:
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case G_MUL:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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if (Op0Size == 128)
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OperandsMapping = getMSAMapping(MF);
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130
test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
Normal file
130
test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
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@ -0,0 +1,130 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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--- |
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define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
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define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
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define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
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define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
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...
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---
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name: mul_v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v16i8
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
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; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<16 x s8>) = G_MUL %4, %3
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G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v8i16
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_H:%[0-9]+]]:msa128h = MULV_H [[LD_H1]], [[LD_H]]
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; P5600: ST_H [[MULV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<8 x s16>) = G_MUL %4, %3
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G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v4i32
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]]
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; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<4 x s32>) = G_MUL %4, %3
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G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v2i64
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_D:%[0-9]+]]:msa128d = MULV_D [[LD_D1]], [[LD_D]]
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; P5600: ST_D [[MULV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<2 x s64>) = G_MUL %4, %3
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G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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122
test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
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122
test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
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@ -0,0 +1,122 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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--- |
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define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
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define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
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define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
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define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
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...
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---
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name: mul_v16i8
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v16i8
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
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; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
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; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(p0) = COPY $a2
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%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:_(<16 x s8>) = G_MUL %4, %3
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G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v8i16
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v8i16
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
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; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
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; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(p0) = COPY $a2
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%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:_(<8 x s16>) = G_MUL %4, %3
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G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v4i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v4i32
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
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; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
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; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(p0) = COPY $a2
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%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:_(<4 x s32>) = G_MUL %4, %3
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G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v2i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v2i64
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
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; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
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; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(p0) = COPY $a2
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%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:_(<2 x s64>) = G_MUL %4, %3
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G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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129
test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
Normal file
129
test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
Normal file
@ -0,0 +1,129 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
|
||||
--- |
|
||||
|
||||
declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
|
||||
define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
|
||||
|
||||
declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
|
||||
define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
|
||||
|
||||
declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
|
||||
define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
|
||||
|
||||
declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
|
||||
define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v16i8_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v16i8_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.b), %3(<16 x s8>), %4(<16 x s8>)
|
||||
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v8i16_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v8i16_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.h), %3(<8 x s16>), %4(<8 x s16>)
|
||||
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v4i32_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v4i32_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.w), %3(<4 x s32>), %4(<4 x s32>)
|
||||
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v2i64_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v2i64_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mulv.d), %3(<2 x s64>), %4(<2 x s64>)
|
||||
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
70
test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
Normal file
70
test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
Normal file
@ -0,0 +1,70 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
|
||||
|
||||
define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
|
||||
; P5600-LABEL: mul_v16i8:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.b $w0, 0($4)
|
||||
; P5600-NEXT: ld.b $w1, 0($5)
|
||||
; P5600-NEXT: mulv.b $w0, $w1, $w0
|
||||
; P5600-NEXT: st.b $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = load <16 x i8>, <16 x i8>* %b, align 16
|
||||
%mul = mul <16 x i8> %1, %0
|
||||
store <16 x i8> %mul, <16 x i8>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
|
||||
; P5600-LABEL: mul_v8i16:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.h $w0, 0($4)
|
||||
; P5600-NEXT: ld.h $w1, 0($5)
|
||||
; P5600-NEXT: mulv.h $w0, $w1, $w0
|
||||
; P5600-NEXT: st.h $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%mul = mul <8 x i16> %1, %0
|
||||
store <8 x i16> %mul, <8 x i16>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
|
||||
; P5600-LABEL: mul_v4i32:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.w $w0, 0($4)
|
||||
; P5600-NEXT: ld.w $w1, 0($5)
|
||||
; P5600-NEXT: mulv.w $w0, $w1, $w0
|
||||
; P5600-NEXT: st.w $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%mul = mul <4 x i32> %1, %0
|
||||
store <4 x i32> %mul, <4 x i32>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
|
||||
; P5600-LABEL: mul_v2i64:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.d $w0, 0($4)
|
||||
; P5600-NEXT: ld.d $w1, 0($5)
|
||||
; P5600-NEXT: mulv.d $w0, $w1, $w0
|
||||
; P5600-NEXT: st.d $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%mul = mul <2 x i64> %1, %0
|
||||
store <2 x i64> %mul, <2 x i64>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
74
test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
Normal file
74
test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll
Normal file
@ -0,0 +1,74 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
|
||||
|
||||
declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
|
||||
define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
|
||||
; P5600-LABEL: mul_v16i8_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.b $w0, 0($4)
|
||||
; P5600-NEXT: ld.b $w1, 0($5)
|
||||
; P5600-NEXT: mulv.b $w0, $w0, $w1
|
||||
; P5600-NEXT: st.b $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = load <16 x i8>, <16 x i8>* %b, align 16
|
||||
%2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)
|
||||
store <16 x i8> %2, <16 x i8>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
|
||||
define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
|
||||
; P5600-LABEL: mul_v8i16_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.h $w0, 0($4)
|
||||
; P5600-NEXT: ld.h $w1, 0($5)
|
||||
; P5600-NEXT: mulv.h $w0, $w0, $w1
|
||||
; P5600-NEXT: st.h $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)
|
||||
store <8 x i16> %2, <8 x i16>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
|
||||
define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
|
||||
; P5600-LABEL: mul_v4i32_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.w $w0, 0($4)
|
||||
; P5600-NEXT: ld.w $w1, 0($5)
|
||||
; P5600-NEXT: mulv.w $w0, $w0, $w1
|
||||
; P5600-NEXT: st.w $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)
|
||||
store <4 x i32> %2, <4 x i32>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
|
||||
define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
|
||||
; P5600-LABEL: mul_v2i64_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.d $w0, 0($4)
|
||||
; P5600-NEXT: ld.d $w1, 0($5)
|
||||
; P5600-NEXT: mulv.d $w0, $w0, $w1
|
||||
; P5600-NEXT: st.d $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)
|
||||
store <2 x i64> %2, <2 x i64>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
126
test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
Normal file
126
test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
Normal file
@ -0,0 +1,126 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
|
||||
--- |
|
||||
|
||||
define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
|
||||
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
|
||||
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
|
||||
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v16i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v16i8
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:fprb(<16 x s8>) = G_MUL [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[MUL]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<16 x s8>) = G_MUL %4, %3
|
||||
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v8i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v8i16
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:fprb(<8 x s16>) = G_MUL [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[MUL]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<8 x s16>) = G_MUL %4, %3
|
||||
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v4i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v4i32
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:fprb(<4 x s32>) = G_MUL [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[MUL]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<4 x s32>) = G_MUL %4, %3
|
||||
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: mul_v2i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: mul_v2i64
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[MUL:%[0-9]+]]:fprb(<2 x s64>) = G_MUL [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[MUL]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<2 x s64>) = G_MUL %4, %3
|
||||
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user