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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00

Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done

llvm-svn: 186280
This commit is contained in:
Stephen Lin 2013-07-14 06:24:09 +00:00
parent 37c18f5cda
commit 7e501cf4c3
937 changed files with 8028 additions and 8028 deletions

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@ -9,7 +9,7 @@
; Add pure 12-bit immediates: ; Add pure 12-bit immediates:
define void @add_small() { define void @add_small() {
; CHECK: add_small: ; CHECK-LABEL: add_small:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32 %val32 = load i32* @var_i32
@ -26,7 +26,7 @@ define void @add_small() {
; Add 12-bit immediates, shifted left by 12 bits ; Add 12-bit immediates, shifted left by 12 bits
define void @add_med() { define void @add_med() {
; CHECK: add_med: ; CHECK-LABEL: add_med:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32 %val32 = load i32* @var_i32
@ -43,7 +43,7 @@ define void @add_med() {
; Subtract 12-bit immediates ; Subtract 12-bit immediates
define void @sub_small() { define void @sub_small() {
; CHECK: sub_small: ; CHECK-LABEL: sub_small:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32 %val32 = load i32* @var_i32
@ -60,7 +60,7 @@ define void @sub_small() {
; Subtract 12-bit immediates, shifted left by 12 bits ; Subtract 12-bit immediates, shifted left by 12 bits
define void @sub_med() { define void @sub_med() {
; CHECK: sub_med: ; CHECK-LABEL: sub_med:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32 %val32 = load i32* @var_i32

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@ -6,7 +6,7 @@
@var64 = global i64 0 @var64 = global i64 0
define void @addsub_i8rhs() { define void @addsub_i8rhs() {
; CHECK: addsub_i8rhs: ; CHECK-LABEL: addsub_i8rhs:
%val8_tmp = load i8* @var8 %val8_tmp = load i8* @var8
%lhs32 = load i32* @var32 %lhs32 = load i32* @var32
%lhs64 = load i64* @var64 %lhs64 = load i64* @var64
@ -81,7 +81,7 @@ end:
} }
define void @addsub_i16rhs() { define void @addsub_i16rhs() {
; CHECK: addsub_i16rhs: ; CHECK-LABEL: addsub_i16rhs:
%val16_tmp = load i16* @var16 %val16_tmp = load i16* @var16
%lhs32 = load i32* @var32 %lhs32 = load i32* @var32
%lhs64 = load i64* @var64 %lhs64 = load i64* @var64
@ -159,7 +159,7 @@ end:
; example), but the remaining instructions are probably not idiomatic ; example), but the remaining instructions are probably not idiomatic
; in the face of "add/sub (shifted register)" so I don't intend to. ; in the face of "add/sub (shifted register)" so I don't intend to.
define void @addsub_i32rhs() { define void @addsub_i32rhs() {
; CHECK: addsub_i32rhs: ; CHECK-LABEL: addsub_i32rhs:
%val32_tmp = load i32* @var32 %val32_tmp = load i32* @var32
%lhs64 = load i64* @var64 %lhs64 = load i64* @var64

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@ -1,7 +1,7 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
define i32 @foo(i32* %var, i1 %cond) { define i32 @foo(i32* %var, i1 %cond) {
; CHECK: foo: ; CHECK-LABEL: foo:
br i1 %cond, label %atomic_ver, label %simple_ver br i1 %cond, label %atomic_ver, label %simple_ver
simple_ver: simple_ver:
%oldval = load i32* %var %oldval = load i32* %var

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@ -6,7 +6,7 @@
; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text] ; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
define i32 @get_globalvar() { define i32 @get_globalvar() {
; CHECK: get_globalvar: ; CHECK-LABEL: get_globalvar:
%val = load i32* @var %val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@ -19,7 +19,7 @@ define i32 @get_globalvar() {
} }
define i32* @get_globalvaraddr() { define i32* @get_globalvaraddr() {
; CHECK: get_globalvaraddr: ; CHECK-LABEL: get_globalvaraddr:
%val = load i32* @var %val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@ -33,7 +33,7 @@ define i32* @get_globalvaraddr() {
@hiddenvar = hidden global i32 0 @hiddenvar = hidden global i32 0
define i32 @get_hiddenvar() { define i32 @get_hiddenvar() {
; CHECK: get_hiddenvar: ; CHECK-LABEL: get_hiddenvar:
%val = load i32* @hiddenvar %val = load i32* @hiddenvar
; CHECK: adrp x[[HI:[0-9]+]], hiddenvar ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
@ -45,7 +45,7 @@ define i32 @get_hiddenvar() {
} }
define i32* @get_hiddenvaraddr() { define i32* @get_hiddenvaraddr() {
; CHECK: get_hiddenvaraddr: ; CHECK-LABEL: get_hiddenvaraddr:
%val = load i32* @hiddenvar %val = load i32* @hiddenvar
; CHECK: adrp [[HI:x[0-9]+]], hiddenvar ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
@ -57,7 +57,7 @@ define i32* @get_hiddenvaraddr() {
} }
define void()* @get_func() { define void()* @get_func() {
; CHECK: get_func: ; CHECK-LABEL: get_func:
ret void()* bitcast(void()*()* @get_func to void()*) ret void()* bitcast(void()*()* @get_func to void()*)
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func

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@ -6,7 +6,7 @@
%struct.foo = type { i8, [2 x i8], i8 } %struct.foo = type { i8, [2 x i8], i8 }
define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone { define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
; CHECK: from_clang: ; CHECK-LABEL: from_clang:
; CHECK: bfi w0, w1, #3, #4 ; CHECK: bfi w0, w1, #3, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret

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@ -3,7 +3,7 @@
@stored_label = global i8* null @stored_label = global i8* null
define void @foo() { define void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
%lab = load i8** @stored_label %lab = load i8** @stored_label
indirectbr i8* %lab, [label %otherlab, label %retlab] indirectbr i8* %lab, [label %otherlab, label %retlab]
; CHECK: adrp {{x[0-9]+}}, stored_label ; CHECK: adrp {{x[0-9]+}}, stored_label

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@ -3,7 +3,7 @@
@var = global float 0.0 @var = global float 0.0
define void @foo() { define void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK: stp d14, d15, [sp ; CHECK: stp d14, d15, [sp
; CHECK: stp d12, d13, [sp ; CHECK: stp d12, d13, [sp

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@ -6,7 +6,7 @@
@var64 = global i64 0 @var64 = global i64 0
define i8* @global_addr() { define i8* @global_addr() {
; CHECK: global_addr: ; CHECK-LABEL: global_addr:
ret i8* @var8 ret i8* @var8
; The movz/movk calculation should end up returned directly in x0. ; The movz/movk calculation should end up returned directly in x0.
; CHECK: movz x0, #:abs_g3:var8 ; CHECK: movz x0, #:abs_g3:var8
@ -17,7 +17,7 @@ define i8* @global_addr() {
} }
define i8 @global_i8() { define i8 @global_i8() {
; CHECK: global_i8: ; CHECK-LABEL: global_i8:
%val = load i8* @var8 %val = load i8* @var8
ret i8 %val ret i8 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
@ -28,7 +28,7 @@ define i8 @global_i8() {
} }
define i16 @global_i16() { define i16 @global_i16() {
; CHECK: global_i16: ; CHECK-LABEL: global_i16:
%val = load i16* @var16 %val = load i16* @var16
ret i16 %val ret i16 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
@ -39,7 +39,7 @@ define i16 @global_i16() {
} }
define i32 @global_i32() { define i32 @global_i32() {
; CHECK: global_i32: ; CHECK-LABEL: global_i32:
%val = load i32* @var32 %val = load i32* @var32
ret i32 %val ret i32 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
@ -50,7 +50,7 @@ define i32 @global_i32() {
} }
define i64 @global_i64() { define i64 @global_i64() {
; CHECK: global_i64: ; CHECK-LABEL: global_i64:
%val = load i64* @var64 %val = load i64* @var64
ret i64 %val ret i64 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64

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@ -4,7 +4,7 @@
@var64 = global i64 0 @var64 = global i64 0
define void @foo() { define void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
%val1 = load volatile i32* @var32 %val1 = load volatile i32* @var32
%tst1 = icmp eq i32 %val1, 0 %tst1 = icmp eq i32 %val1, 0

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@ -4,7 +4,7 @@
@var64 = global i64 0 @var64 = global i64 0
define void @rev_i32() { define void @rev_i32() {
; CHECK: rev_i32: ; CHECK-LABEL: rev_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp) %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
@ -13,7 +13,7 @@ define void @rev_i32() {
} }
define void @rev_i64() { define void @rev_i64() {
; CHECK: rev_i64: ; CHECK-LABEL: rev_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp) %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
@ -22,7 +22,7 @@ define void @rev_i64() {
} }
define void @rev32_i64() { define void @rev32_i64() {
; CHECK: rev32_i64: ; CHECK-LABEL: rev32_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val1_tmp = shl i64 %val0_tmp, 32 %val1_tmp = shl i64 %val0_tmp, 32
%val5_tmp = sub i64 64, 32 %val5_tmp = sub i64 64, 32
@ -35,7 +35,7 @@ define void @rev32_i64() {
} }
define void @rev16_i32() { define void @rev16_i32() {
; CHECK: rev16_i32: ; CHECK-LABEL: rev16_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val1_tmp = shl i32 %val0_tmp, 16 %val1_tmp = shl i32 %val0_tmp, 16
%val2_tmp = lshr i32 %val0_tmp, 16 %val2_tmp = lshr i32 %val0_tmp, 16
@ -47,7 +47,7 @@ define void @rev16_i32() {
} }
define void @clz_zerodef_i32() { define void @clz_zerodef_i32() {
; CHECK: clz_zerodef_i32: ; CHECK-LABEL: clz_zerodef_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0) %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
@ -56,7 +56,7 @@ define void @clz_zerodef_i32() {
} }
define void @clz_zerodef_i64() { define void @clz_zerodef_i64() {
; CHECK: clz_zerodef_i64: ; CHECK-LABEL: clz_zerodef_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0) %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
@ -65,7 +65,7 @@ define void @clz_zerodef_i64() {
} }
define void @clz_zeroundef_i32() { define void @clz_zeroundef_i32() {
; CHECK: clz_zeroundef_i32: ; CHECK-LABEL: clz_zeroundef_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1) %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
@ -74,7 +74,7 @@ define void @clz_zeroundef_i32() {
} }
define void @clz_zeroundef_i64() { define void @clz_zeroundef_i64() {
; CHECK: clz_zeroundef_i64: ; CHECK-LABEL: clz_zeroundef_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1) %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
@ -83,7 +83,7 @@ define void @clz_zeroundef_i64() {
} }
define void @cttz_zerodef_i32() { define void @cttz_zerodef_i32() {
; CHECK: cttz_zerodef_i32: ; CHECK-LABEL: cttz_zerodef_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0) %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@ -93,7 +93,7 @@ define void @cttz_zerodef_i32() {
} }
define void @cttz_zerodef_i64() { define void @cttz_zerodef_i64() {
; CHECK: cttz_zerodef_i64: ; CHECK-LABEL: cttz_zerodef_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0) %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@ -103,7 +103,7 @@ define void @cttz_zerodef_i64() {
} }
define void @cttz_zeroundef_i32() { define void @cttz_zeroundef_i32() {
; CHECK: cttz_zeroundef_i32: ; CHECK-LABEL: cttz_zeroundef_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1) %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@ -113,7 +113,7 @@ define void @cttz_zeroundef_i32() {
} }
define void @cttz_zeroundef_i64() { define void @cttz_zeroundef_i64() {
; CHECK: cttz_zeroundef_i64: ; CHECK-LABEL: cttz_zeroundef_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1) %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@ -125,7 +125,7 @@ define void @cttz_zeroundef_i64() {
; These two are just compilation tests really: the operation's set to Expand in ; These two are just compilation tests really: the operation's set to Expand in
; ISelLowering. ; ISelLowering.
define void @ctpop_i32() { define void @ctpop_i32() {
; CHECK: ctpop_i32: ; CHECK-LABEL: ctpop_i32:
%val0_tmp = load i32* @var32 %val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp) %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
store volatile i32 %val4_tmp, i32* @var32 store volatile i32 %val4_tmp, i32* @var32
@ -133,7 +133,7 @@ define void @ctpop_i32() {
} }
define void @ctpop_i64() { define void @ctpop_i64() {
; CHECK: ctpop_i64: ; CHECK-LABEL: ctpop_i64:
%val0_tmp = load i64* @var64 %val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp) %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
store volatile i64 %val4_tmp, i64* @var64 store volatile i64 %val4_tmp, i64* @var64

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@ -6,7 +6,7 @@
@var64_1 = global i64 0 @var64_1 = global i64 0
define void @rorv_i64() { define void @rorv_i64() {
; CHECK: rorv_i64: ; CHECK-LABEL: rorv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val2_tmp = sub i64 64, %val1_tmp %val2_tmp = sub i64 64, %val1_tmp
@ -19,7 +19,7 @@ define void @rorv_i64() {
} }
define void @asrv_i64() { define void @asrv_i64() {
; CHECK: asrv_i64: ; CHECK-LABEL: asrv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val4_tmp = ashr i64 %val0_tmp, %val1_tmp %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
@ -29,7 +29,7 @@ define void @asrv_i64() {
} }
define void @lsrv_i64() { define void @lsrv_i64() {
; CHECK: lsrv_i64: ; CHECK-LABEL: lsrv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val4_tmp = lshr i64 %val0_tmp, %val1_tmp %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@ -39,7 +39,7 @@ define void @lsrv_i64() {
} }
define void @lslv_i64() { define void @lslv_i64() {
; CHECK: lslv_i64: ; CHECK-LABEL: lslv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val4_tmp = shl i64 %val0_tmp, %val1_tmp %val4_tmp = shl i64 %val0_tmp, %val1_tmp
@ -49,7 +49,7 @@ define void @lslv_i64() {
} }
define void @udiv_i64() { define void @udiv_i64() {
; CHECK: udiv_i64: ; CHECK-LABEL: udiv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val4_tmp = udiv i64 %val0_tmp, %val1_tmp %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
@ -59,7 +59,7 @@ define void @udiv_i64() {
} }
define void @sdiv_i64() { define void @sdiv_i64() {
; CHECK: sdiv_i64: ; CHECK-LABEL: sdiv_i64:
%val0_tmp = load i64* @var64_0 %val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1 %val1_tmp = load i64* @var64_1
%val4_tmp = sdiv i64 %val0_tmp, %val1_tmp %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
@ -70,7 +70,7 @@ define void @sdiv_i64() {
define void @lsrv_i32() { define void @lsrv_i32() {
; CHECK: lsrv_i32: ; CHECK-LABEL: lsrv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1 %val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp %val2_tmp = add i32 1, %val1_tmp
@ -81,7 +81,7 @@ define void @lsrv_i32() {
} }
define void @lslv_i32() { define void @lslv_i32() {
; CHECK: lslv_i32: ; CHECK-LABEL: lslv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1 %val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp %val2_tmp = add i32 1, %val1_tmp
@ -92,7 +92,7 @@ define void @lslv_i32() {
} }
define void @rorv_i32() { define void @rorv_i32() {
; CHECK: rorv_i32: ; CHECK-LABEL: rorv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val6_tmp = load i32* @var32_1 %val6_tmp = load i32* @var32_1
%val1_tmp = add i32 1, %val6_tmp %val1_tmp = add i32 1, %val6_tmp
@ -106,7 +106,7 @@ define void @rorv_i32() {
} }
define void @asrv_i32() { define void @asrv_i32() {
; CHECK: asrv_i32: ; CHECK-LABEL: asrv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1 %val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp %val2_tmp = add i32 1, %val1_tmp
@ -117,7 +117,7 @@ define void @asrv_i32() {
} }
define void @sdiv_i32() { define void @sdiv_i32() {
; CHECK: sdiv_i32: ; CHECK-LABEL: sdiv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1 %val1_tmp = load i32* @var32_1
%val4_tmp = sdiv i32 %val0_tmp, %val1_tmp %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
@ -127,7 +127,7 @@ define void @sdiv_i32() {
} }
define void @udiv_i32() { define void @udiv_i32() {
; CHECK: udiv_i32: ; CHECK-LABEL: udiv_i32:
%val0_tmp = load i32* @var32_0 %val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1 %val1_tmp = load i32* @var32_1
%val4_tmp = udiv i32 %val0_tmp, %val1_tmp %val4_tmp = udiv i32 %val0_tmp, %val1_tmp

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@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i64 @ror_i64(i64 %in) { define i64 @ror_i64(i64 %in) {
; CHECK: ror_i64: ; CHECK-LABEL: ror_i64:
%left = shl i64 %in, 19 %left = shl i64 %in, 19
%right = lshr i64 %in, 45 %right = lshr i64 %in, 45
%val5 = or i64 %left, %right %val5 = or i64 %left, %right
@ -10,7 +10,7 @@ define i64 @ror_i64(i64 %in) {
} }
define i32 @ror_i32(i32 %in) { define i32 @ror_i32(i32 %in) {
; CHECK: ror_i32: ; CHECK-LABEL: ror_i32:
%left = shl i32 %in, 9 %left = shl i32 %in, 9
%right = lshr i32 %in, 23 %right = lshr i32 %in, 23
%val5 = or i32 %left, %right %val5 = or i32 %left, %right
@ -19,7 +19,7 @@ define i32 @ror_i32(i32 %in) {
} }
define i32 @extr_i32(i32 %lhs, i32 %rhs) { define i32 @extr_i32(i32 %lhs, i32 %rhs) {
; CHECK: extr_i32: ; CHECK-LABEL: extr_i32:
%left = shl i32 %lhs, 6 %left = shl i32 %lhs, 6
%right = lshr i32 %rhs, 26 %right = lshr i32 %rhs, 26
%val = or i32 %left, %right %val = or i32 %left, %right
@ -31,7 +31,7 @@ define i32 @extr_i32(i32 %lhs, i32 %rhs) {
} }
define i64 @extr_i64(i64 %lhs, i64 %rhs) { define i64 @extr_i64(i64 %lhs, i64 %rhs) {
; CHECK: extr_i64: ; CHECK-LABEL: extr_i64:
%right = lshr i64 %rhs, 40 %right = lshr i64 %rhs, 40
%left = shl i64 %lhs, 24 %left = shl i64 %lhs, 24
%val = or i64 %right, %left %val = or i64 %right, %left
@ -45,7 +45,7 @@ define i64 @extr_i64(i64 %lhs, i64 %rhs) {
; Regression test: a bad experimental pattern crept into git which optimised ; Regression test: a bad experimental pattern crept into git which optimised
; this pattern to a single EXTR. ; this pattern to a single EXTR.
define i32 @extr_regress(i32 %a, i32 %b) { define i32 @extr_regress(i32 %a, i32 %b) {
; CHECK: extr_regress: ; CHECK-LABEL: extr_regress:
%sh1 = shl i32 %a, 14 %sh1 = shl i32 %a, 14
%sh2 = lshr i32 %b, 14 %sh2 = lshr i32 %b, 14

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@ -7,7 +7,7 @@
declare fastcc void @will_pop([8 x i32], i32 %val) declare fastcc void @will_pop([8 x i32], i32 %val)
define fastcc void @foo(i32 %in) { define fastcc void @foo(i32 %in) {
; CHECK: foo: ; CHECK-LABEL: foo:
%addr = alloca i8, i32 %in %addr = alloca i8, i32 %in
@ -34,7 +34,7 @@ define fastcc void @foo(i32 %in) {
declare void @wont_pop([8 x i32], i32 %val) declare void @wont_pop([8 x i32], i32 %val)
define void @foo1(i32 %in) { define void @foo1(i32 %in) {
; CHECK: foo1: ; CHECK-LABEL: foo1:
%addr = alloca i8, i32 %in %addr = alloca i8, i32 %in
; Normal frame setup again ; Normal frame setup again

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@ -5,10 +5,10 @@
; stack, so try to make sure this is respected. ; stack, so try to make sure this is respected.
define fastcc void @func_stack0() { define fastcc void @func_stack0() {
; CHECK: func_stack0: ; CHECK-LABEL: func_stack0:
; CHECK: sub sp, sp, #48 ; CHECK: sub sp, sp, #48
; CHECK-TAIL: func_stack0: ; CHECK-TAIL-LABEL: func_stack0:
; CHECK-TAIL: sub sp, sp, #48 ; CHECK-TAIL: sub sp, sp, #48
@ -45,10 +45,10 @@ define fastcc void @func_stack0() {
} }
define fastcc void @func_stack8([8 x i32], i32 %stacked) { define fastcc void @func_stack8([8 x i32], i32 %stacked) {
; CHECK: func_stack8: ; CHECK-LABEL: func_stack8:
; CHECK: sub sp, sp, #48 ; CHECK: sub sp, sp, #48
; CHECK-TAIL: func_stack8: ; CHECK-TAIL-LABEL: func_stack8:
; CHECK-TAIL: sub sp, sp, #48 ; CHECK-TAIL: sub sp, sp, #48
@ -84,10 +84,10 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) {
} }
define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) { define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
; CHECK: func_stack32: ; CHECK-LABEL: func_stack32:
; CHECK: sub sp, sp, #48 ; CHECK: sub sp, sp, #48
; CHECK-TAIL: func_stack32: ; CHECK-TAIL-LABEL: func_stack32:
; CHECK-TAIL: sub sp, sp, #48 ; CHECK-TAIL: sub sp, sp, #48

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@ -26,7 +26,7 @@ declare float @nearbyintf(float) readonly
declare double @nearbyint(double) readonly declare double @nearbyint(double) readonly
define void @simple_float() { define void @simple_float() {
; CHECK: simple_float: ; CHECK-LABEL: simple_float:
%val1 = load volatile float* @varfloat %val1 = load volatile float* @varfloat
%valabs = call float @fabsf(float %val1) %valabs = call float @fabsf(float %val1)
@ -65,7 +65,7 @@ define void @simple_float() {
} }
define void @simple_double() { define void @simple_double() {
; CHECK: simple_double: ; CHECK-LABEL: simple_double:
%val1 = load volatile double* @vardouble %val1 = load volatile double* @vardouble
%valabs = call double @fabs(double %val1) %valabs = call double @fabs(double %val1)
@ -104,7 +104,7 @@ define void @simple_double() {
} }
define void @converts() { define void @converts() {
; CHECK: converts: ; CHECK-LABEL: converts:
%val16 = load volatile half* @varhalf %val16 = load volatile half* @varhalf
%val32 = load volatile float* @varfloat %val32 = load volatile float* @varfloat

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@ -46,7 +46,7 @@ define float @test_fnmsub(float %a, float %b, float %c) {
define double @testd_fmadd(double %a, double %b, double %c) { define double @testd_fmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmadd: ; CHECK-LABEL: testd_fmadd:
; CHECK-NOFAST: testd_fmadd: ; CHECK-NOFAST-LABEL: testd_fmadd:
%val = call double @llvm.fma.f64(double %a, double %b, double %c) %val = call double @llvm.fma.f64(double %a, double %b, double %c)
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} ; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@ -55,7 +55,7 @@ define double @testd_fmadd(double %a, double %b, double %c) {
define double @testd_fmsub(double %a, double %b, double %c) { define double @testd_fmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmsub: ; CHECK-LABEL: testd_fmsub:
; CHECK-NOFAST: testd_fmsub: ; CHECK-NOFAST-LABEL: testd_fmsub:
%nega = fsub double -0.0, %a %nega = fsub double -0.0, %a
%val = call double @llvm.fma.f64(double %nega, double %b, double %c) %val = call double @llvm.fma.f64(double %nega, double %b, double %c)
; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@ -65,7 +65,7 @@ define double @testd_fmsub(double %a, double %b, double %c) {
define double @testd_fnmadd(double %a, double %b, double %c) { define double @testd_fnmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmadd: ; CHECK-LABEL: testd_fnmadd:
; CHECK-NOFAST: testd_fnmadd: ; CHECK-NOFAST-LABEL: testd_fnmadd:
%negc = fsub double -0.0, %c %negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %a, double %b, double %negc) %val = call double @llvm.fma.f64(double %a, double %b, double %negc)
; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@ -75,7 +75,7 @@ define double @testd_fnmadd(double %a, double %b, double %c) {
define double @testd_fnmsub(double %a, double %b, double %c) { define double @testd_fnmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmsub: ; CHECK-LABEL: testd_fnmsub:
; CHECK-NOFAST: testd_fnmsub: ; CHECK-NOFAST-LABEL: testd_fnmsub:
%nega = fsub double -0.0, %a %nega = fsub double -0.0, %a
%negc = fsub double -0.0, %c %negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %nega, double %b, double %negc) %val = call double @llvm.fma.f64(double %nega, double %b, double %negc)

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@ -4,7 +4,7 @@
@varf64 = global double 0.0 @varf64 = global double 0.0
define void @check_float() { define void @check_float() {
; CHECK: check_float: ; CHECK-LABEL: check_float:
%val = load float* @varf32 %val = load float* @varf32
%newval1 = fadd float %val, 8.5 %newval1 = fadd float %val, 8.5
@ -19,7 +19,7 @@ define void @check_float() {
} }
define void @check_double() { define void @check_double() {
; CHECK: check_double: ; CHECK-LABEL: check_double:
%val = load double* @varf64 %val = load double* @varf64
%newval1 = fadd double %val, 8.5 %newval1 = fadd double %val, 8.5

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@ -11,7 +11,7 @@
@varstruct = global %myStruct zeroinitializer @varstruct = global %myStruct zeroinitializer
define void @take_i8s(i8 %val1, i8 %val2) { define void @take_i8s(i8 %val1, i8 %val2) {
; CHECK: take_i8s: ; CHECK-LABEL: take_i8s:
store i8 %val2, i8* @var8 store i8 %val2, i8* @var8
; Not using w1 may be technically allowed, but it would indicate a ; Not using w1 may be technically allowed, but it would indicate a
; problem in itself. ; problem in itself.
@ -20,7 +20,7 @@ define void @take_i8s(i8 %val1, i8 %val2) {
} }
define void @add_floats(float %val1, float %val2) { define void @add_floats(float %val1, float %val2) {
; CHECK: add_floats: ; CHECK-LABEL: add_floats:
%newval = fadd float %val1, %val2 %newval = fadd float %val1, %val2
; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1 ; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
store float %newval, float* @varfloat store float %newval, float* @varfloat
@ -31,7 +31,7 @@ define void @add_floats(float %val1, float %val2) {
; byval pointers should be allocated to the stack and copied as if ; byval pointers should be allocated to the stack and copied as if
; with memcpy. ; with memcpy.
define void @take_struct(%myStruct* byval %structval) { define void @take_struct(%myStruct* byval %structval) {
; CHECK: take_struct: ; CHECK-LABEL: take_struct:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@ -51,7 +51,7 @@ define void @take_struct(%myStruct* byval %structval) {
; %structval should be at sp + 16 ; %structval should be at sp + 16
define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
; CHECK: check_byval_align: ; CHECK-LABEL: check_byval_align:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@ -72,7 +72,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
} }
define i32 @return_int() { define i32 @return_int() {
; CHECK: return_int: ; CHECK-LABEL: return_int:
%val = load i32* @var32 %val = load i32* @var32
ret i32 %val ret i32 %val
; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32] ; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
@ -81,7 +81,7 @@ define i32 @return_int() {
} }
define double @return_double() { define double @return_double() {
; CHECK: return_double: ; CHECK-LABEL: return_double:
ret double 3.14 ret double 3.14
; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI ; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
} }
@ -90,7 +90,7 @@ define double @return_double() {
; small enough to go into registers. Not all that pretty, but it ; small enough to go into registers. Not all that pretty, but it
; works. ; works.
define [2 x i64] @return_struct() { define [2 x i64] @return_struct() {
; CHECK: return_struct: ; CHECK-LABEL: return_struct:
%addr = bitcast %myStruct* @varstruct to [2 x i64]* %addr = bitcast %myStruct* @varstruct to [2 x i64]*
%val = load [2 x i64]* %addr %val = load [2 x i64]* %addr
ret [2 x i64] %val ret [2 x i64] %val
@ -107,7 +107,7 @@ define [2 x i64] @return_struct() {
; structs larger than 16 bytes, but C semantics can still be provided ; structs larger than 16 bytes, but C semantics can still be provided
; if LLVM does it to %myStruct too. So this is the simplest check ; if LLVM does it to %myStruct too. So this is the simplest check
define void @return_large_struct(%myStruct* sret %retval) { define void @return_large_struct(%myStruct* sret %retval) {
; CHECK: return_large_struct: ; CHECK-LABEL: return_large_struct:
%addr0 = getelementptr %myStruct* %retval, i64 0, i32 0 %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
%addr1 = getelementptr %myStruct* %retval, i64 0, i32 1 %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
%addr2 = getelementptr %myStruct* %retval, i64 0, i32 2 %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
@ -128,7 +128,7 @@ define void @return_large_struct(%myStruct* sret %retval) {
define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval %struct, i32* byval %stacked, i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
double %notstacked) { double %notstacked) {
; CHECK: struct_on_stack: ; CHECK-LABEL: struct_on_stack:
%addr = getelementptr %myStruct* %struct, i64 0, i32 0 %addr = getelementptr %myStruct* %struct, i64 0, i32 0
%val64 = load i64* %addr %val64 = load i64* %addr
store i64 %val64, i64* @var64 store i64 %val64, i64* @var64
@ -148,7 +148,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7, float %var4, float %var5, float %var6, float %var7,
float %var8) { float %var8) {
; CHECK: stacked_fpu: ; CHECK-LABEL: stacked_fpu:
store float %var8, float* @varfloat store float %var8, float* @varfloat
; Beware as above: the offset would be different on big-endian ; Beware as above: the offset would be different on big-endian
; machines if the first ldr were changed to use s-registers. ; machines if the first ldr were changed to use s-registers.

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@ -17,7 +17,7 @@ declare void @take_i8s(i8 %val1, i8 %val2)
declare void @take_floats(float %val1, float %val2) declare void @take_floats(float %val1, float %val2)
define void @simple_args() { define void @simple_args() {
; CHECK: simple_args: ; CHECK-LABEL: simple_args:
%char1 = load i8* @var8 %char1 = load i8* @var8
%char2 = load i8* @var8_2 %char2 = load i8* @var8_2
call void @take_i8s(i8 %char1, i8 %char2) call void @take_i8s(i8 %char1, i8 %char2)
@ -41,7 +41,7 @@ declare [2 x i64] @return_smallstruct()
declare void @return_large_struct(%myStruct* sret %retval) declare void @return_large_struct(%myStruct* sret %retval)
define void @simple_rets() { define void @simple_rets() {
; CHECK: simple_rets: ; CHECK-LABEL: simple_rets:
%int = call i32 @return_int() %int = call i32 @return_int()
store i32 %int, i32* @var32 store i32 %int, i32* @var32
@ -106,7 +106,7 @@ declare void @check_i128_regalign(i32 %val0, i128 %val1)
define void @check_i128_align() { define void @check_i128_align() {
; CHECK: check_i128_align: ; CHECK-LABEL: check_i128_align:
%val = load i128* @var128 %val = load i128* @var128
call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3, call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7,
@ -130,7 +130,7 @@ define void @check_i128_align() {
@fptr = global void()* null @fptr = global void()* null
define void @check_indirect_call() { define void @check_indirect_call() {
; CHECK: check_indirect_call: ; CHECK-LABEL: check_indirect_call:
%func = load void()** @fptr %func = load void()** @fptr
call void %func() call void %func()
; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr] ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]

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@ -13,7 +13,7 @@ declare void @consume(i32)
declare void @func() declare void @func()
define void @foo() nounwind { define void @foo() nounwind {
; CHECK: foo: ; CHECK-LABEL: foo:
entry: entry:
call void @consume(i32 ptrtoint (void ()* @func to i32)) call void @consume(i32 ptrtoint (void ()* @func to i32))
; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func

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@ -5,7 +5,7 @@
@var = global %struct zeroinitializer @var = global %struct zeroinitializer
define i64 @check_size() { define i64 @check_size() {
; CHECK: check_size: ; CHECK-LABEL: check_size:
%starti = ptrtoint %struct* @var to i64 %starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 1 %endp = getelementptr %struct* @var, i64 1
@ -17,7 +17,7 @@ define i64 @check_size() {
} }
define i64 @check_field() { define i64 @check_field() {
; CHECK: check_field: ; CHECK-LABEL: check_field:
%starti = ptrtoint %struct* @var to i64 %starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 0, i32 1 %endp = getelementptr %struct* @var, i64 0, i32 1

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@ -9,7 +9,7 @@
@var_double = global double 0.0 @var_double = global double 0.0
define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) { define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_8bit: ; CHECK-LABEL: ldst_8bit:
%addr8_sxtw = getelementptr i8* %base, i32 %off32 %addr8_sxtw = getelementptr i8* %base, i32 %off32
%val8_sxtw = load volatile i8* %addr8_sxtw %val8_sxtw = load volatile i8* %addr8_sxtw
@ -37,7 +37,7 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) { define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_16bit: ; CHECK-LABEL: ldst_16bit:
%addr8_sxtwN = getelementptr i16* %base, i32 %off32 %addr8_sxtwN = getelementptr i16* %base, i32 %off32
%val8_sxtwN = load volatile i16* %addr8_sxtwN %val8_sxtwN = load volatile i16* %addr8_sxtwN
@ -91,7 +91,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
} }
define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) { define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_32bit: ; CHECK-LABEL: ldst_32bit:
%addr_sxtwN = getelementptr i32* %base, i32 %off32 %addr_sxtwN = getelementptr i32* %base, i32 %off32
%val_sxtwN = load volatile i32* %addr_sxtwN %val_sxtwN = load volatile i32* %addr_sxtwN
@ -143,7 +143,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
} }
define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) { define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_64bit: ; CHECK-LABEL: ldst_64bit:
%addr_sxtwN = getelementptr i64* %base, i32 %off32 %addr_sxtwN = getelementptr i64* %base, i32 %off32
%val_sxtwN = load volatile i64* %addr_sxtwN %val_sxtwN = load volatile i64* %addr_sxtwN
@ -191,7 +191,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
} }
define void @ldst_float(float* %base, i32 %off32, i64 %off64) { define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_float: ; CHECK-LABEL: ldst_float:
%addr_sxtwN = getelementptr float* %base, i32 %off32 %addr_sxtwN = getelementptr float* %base, i32 %off32
%val_sxtwN = load volatile float* %addr_sxtwN %val_sxtwN = load volatile float* %addr_sxtwN
@ -238,7 +238,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
} }
define void @ldst_double(double* %base, i32 %off32, i64 %off64) { define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_double: ; CHECK-LABEL: ldst_double:
%addr_sxtwN = getelementptr double* %base, i32 %off32 %addr_sxtwN = getelementptr double* %base, i32 %off32
%val_sxtwN = load volatile double* %addr_sxtwN %val_sxtwN = load volatile double* %addr_sxtwN
@ -286,7 +286,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) { define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
; CHECK: ldst_128bit: ; CHECK-LABEL: ldst_128bit:
%addr_sxtwN = getelementptr fp128* %base, i32 %off32 %addr_sxtwN = getelementptr fp128* %base, i32 %off32
%val_sxtwN = load volatile fp128* %addr_sxtwN %val_sxtwN = load volatile fp128* %addr_sxtwN

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@ -11,7 +11,7 @@
@varptr = global i8* null @varptr = global i8* null
define void @ldst_8bit() { define void @ldst_8bit() {
; CHECK: ldst_8bit: ; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we ; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering. ; promote i8 during lowering.
@ -72,7 +72,7 @@ define void @ldst_8bit() {
} }
define void @ldst_16bit() { define void @ldst_16bit() {
; CHECK: ldst_16bit: ; CHECK-LABEL: ldst_16bit:
; No architectural support for loads to 16-bit or 16-bit since we ; No architectural support for loads to 16-bit or 16-bit since we
; promote i16 during lowering. ; promote i16 during lowering.
@ -140,7 +140,7 @@ define void @ldst_16bit() {
} }
define void @ldst_32bit() { define void @ldst_32bit() {
; CHECK: ldst_32bit: ; CHECK-LABEL: ldst_32bit:
%addr_8bit = load i8** @varptr %addr_8bit = load i8** @varptr
@ -186,7 +186,7 @@ define void @ldst_32bit() {
} }
define void @ldst_float() { define void @ldst_float() {
; CHECK: ldst_float: ; CHECK-LABEL: ldst_float:
%addr_8bit = load i8** @varptr %addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 -5 %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
@ -202,7 +202,7 @@ define void @ldst_float() {
} }
define void @ldst_double() { define void @ldst_double() {
; CHECK: ldst_double: ; CHECK-LABEL: ldst_double:
%addr_8bit = load i8** @varptr %addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 4 %addrfp_8 = getelementptr i8* %addr_8bit, i64 4

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@ -9,7 +9,7 @@
@var_double = global double 0.0 @var_double = global double 0.0
define void @ldst_8bit() { define void @ldst_8bit() {
; CHECK: ldst_8bit: ; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we ; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering. ; promote i8 during lowering.
@ -63,7 +63,7 @@ define void @ldst_8bit() {
} }
define void @ldst_16bit() { define void @ldst_16bit() {
; CHECK: ldst_16bit: ; CHECK-LABEL: ldst_16bit:
; No architectural support for load volatiles to 16-bit promote i16 during ; No architectural support for load volatiles to 16-bit promote i16 during
; lowering. ; lowering.
@ -117,7 +117,7 @@ define void @ldst_16bit() {
} }
define void @ldst_32bit() { define void @ldst_32bit() {
; CHECK: ldst_32bit: ; CHECK-LABEL: ldst_32bit:
; Straight 32-bit load/store ; Straight 32-bit load/store
%val32_noext = load volatile i32* @var_32bit %val32_noext = load volatile i32* @var_32bit
@ -225,7 +225,7 @@ define void @ldst_complex_offsets() {
} }
define void @ldst_float() { define void @ldst_float() {
; CHECK: ldst_float: ; CHECK-LABEL: ldst_float:
%valfp = load volatile float* @var_float %valfp = load volatile float* @var_float
; CHECK: adrp {{x[0-9]+}}, var_float ; CHECK: adrp {{x[0-9]+}}, var_float
@ -238,7 +238,7 @@ define void @ldst_float() {
} }
define void @ldst_double() { define void @ldst_double() {
; CHECK: ldst_double: ; CHECK-LABEL: ldst_double:
%valfp = load volatile double* @var_double %valfp = load volatile double* @var_double
; CHECK: adrp {{x[0-9]+}}, var_double ; CHECK: adrp {{x[0-9]+}}, var_double

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@ -5,7 +5,7 @@
@var64 = global i64 0 @var64 = global i64 0
define void @foo() { define void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
%val32 = load i32* @var32 %val32 = load i32* @var32
%val64 = load i64* @var64 %val64 = load i64* @var64
@ -60,7 +60,7 @@ define void @foo() {
@vardouble = global double 0.0 @vardouble = global double 0.0
define void @floating_lits() { define void @floating_lits() {
; CHECK: floating_lits: ; CHECK-LABEL: floating_lits:
%floatval = load float* @varfloat %floatval = load float* @varfloat
%newfloat = fadd float %floatval, 128.0 %newfloat = fadd float %floatval, 128.0

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@ -24,7 +24,7 @@ define void @trivial_func() nounwind {
} }
define void @trivial_fp_func() { define void @trivial_fp_func() {
; CHECK-WITHFP: trivial_fp_func: ; CHECK-WITHFP-LABEL: trivial_fp_func:
; CHECK-WITHFP: sub sp, sp, #16 ; CHECK-WITHFP: sub sp, sp, #16
; CHECK-WITHFP: stp x29, x30, [sp] ; CHECK-WITHFP: stp x29, x30, [sp]
@ -43,7 +43,7 @@ define void @trivial_fp_func() {
define void @stack_local() { define void @stack_local() {
%local_var = alloca i64 %local_var = alloca i64
; CHECK: stack_local: ; CHECK-LABEL: stack_local:
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
%val = load i64* @var %val = load i64* @var

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@ -7,7 +7,7 @@
@var2_64 = global i64 0 @var2_64 = global i64 0
define void @logical_32bit() { define void @logical_32bit() {
; CHECK: logical_32bit: ; CHECK-LABEL: logical_32bit:
%val1 = load i32* @var1_32 %val1 = load i32* @var1_32
%val2 = load i32* @var2_32 %val2 = load i32* @var2_32
@ -97,7 +97,7 @@ define void @logical_32bit() {
} }
define void @logical_64bit() { define void @logical_64bit() {
; CHECK: logical_64bit: ; CHECK-LABEL: logical_64bit:
%val1 = load i64* @var1_64 %val1 = load i64* @var1_64
%val2 = load i64* @var2_64 %val2 = load i64* @var2_64
@ -190,7 +190,7 @@ define void @logical_64bit() {
} }
define void @flag_setting() { define void @flag_setting() {
; CHECK: flag_setting: ; CHECK-LABEL: flag_setting:
%val1 = load i64* @var1_64 %val1 = load i64* @var1_64
%val2 = load i64* @var2_64 %val2 = load i64* @var2_64

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@ -4,7 +4,7 @@
declare void @bar() declare void @bar()
define void @foo() { define void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
%func = load void()** @var %func = load void()** @var
; Calling a function encourages @foo to use a callee-saved register, ; Calling a function encourages @foo to use a callee-saved register,

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@ -5,7 +5,7 @@ declare void @callee_stack8([8 x i32], i64)
declare void @callee_stack16([8 x i32], i64, i64) declare void @callee_stack16([8 x i32], i64, i64)
define void @caller_to0_from0() nounwind { define void @caller_to0_from0() nounwind {
; CHECK: caller_to0_from0: ; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB ; CHECK-NEXT: // BB
tail call void @callee_stack0() tail call void @callee_stack0()
ret void ret void
@ -13,7 +13,7 @@ define void @caller_to0_from0() nounwind {
} }
define void @caller_to0_from8([8 x i32], i64) nounwind{ define void @caller_to0_from8([8 x i32], i64) nounwind{
; CHECK: caller_to0_from8: ; CHECK-LABEL: caller_to0_from8:
; CHECK-NEXT: // BB ; CHECK-NEXT: // BB
tail call void @callee_stack0() tail call void @callee_stack0()
@ -22,7 +22,7 @@ define void @caller_to0_from8([8 x i32], i64) nounwind{
} }
define void @caller_to8_from0() { define void @caller_to8_from0() {
; CHECK: caller_to8_from0: ; CHECK-LABEL: caller_to8_from0:
; Caller isn't going to clean up any extra stack we allocate, so it ; Caller isn't going to clean up any extra stack we allocate, so it
; can't be a tail call. ; can't be a tail call.
@ -32,7 +32,7 @@ define void @caller_to8_from0() {
} }
define void @caller_to8_from8([8 x i32], i64 %a) { define void @caller_to8_from8([8 x i32], i64 %a) {
; CHECK: caller_to8_from8: ; CHECK-LABEL: caller_to8_from8:
; CHECK-NOT: sub sp, sp, ; CHECK-NOT: sub sp, sp,
; This should reuse our stack area for the 42 ; This should reuse our stack area for the 42
@ -43,7 +43,7 @@ define void @caller_to8_from8([8 x i32], i64 %a) {
} }
define void @caller_to16_from8([8 x i32], i64 %a) { define void @caller_to16_from8([8 x i32], i64 %a) {
; CHECK: caller_to16_from8: ; CHECK-LABEL: caller_to16_from8:
; Shouldn't be a tail call: we can't use SP+8 because our caller might ; Shouldn't be a tail call: we can't use SP+8 because our caller might
; have something there. This may sound obvious but implementation does ; have something there. This may sound obvious but implementation does
@ -54,7 +54,7 @@ define void @caller_to16_from8([8 x i32], i64 %a) {
} }
define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) { define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
; CHECK: caller_to8_from24: ; CHECK-LABEL: caller_to8_from24:
; CHECK-NOT: sub sp, sp ; CHECK-NOT: sub sp, sp
; Reuse our area, putting "42" at incoming sp ; Reuse our area, putting "42" at incoming sp
@ -65,7 +65,7 @@ define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
} }
define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
; CHECK: caller_to16_from16: ; CHECK-LABEL: caller_to16_from16:
; CHECK-NOT: sub sp, sp, ; CHECK-NOT: sub sp, sp,
; Here we want to make sure that both loads happen before the stores: ; Here we want to make sure that both loads happen before the stores:
@ -85,7 +85,7 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
@func = global void(i32)* null @func = global void(i32)* null
define void @indirect_tail() { define void @indirect_tail() {
; CHECK: indirect_tail: ; CHECK-LABEL: indirect_tail:
; CHECK-NOT: sub sp, sp ; CHECK-NOT: sub sp, sp
%fptr = load void(i32)** @func %fptr = load void(i32)** @func

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@ -5,7 +5,7 @@ declare fastcc void @callee_stack8([8 x i32], i64)
declare fastcc void @callee_stack16([8 x i32], i64, i64) declare fastcc void @callee_stack16([8 x i32], i64, i64)
define fastcc void @caller_to0_from0() nounwind { define fastcc void @caller_to0_from0() nounwind {
; CHECK: caller_to0_from0: ; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB ; CHECK-NEXT: // BB
tail call fastcc void @callee_stack0() tail call fastcc void @callee_stack0()
ret void ret void
@ -13,7 +13,7 @@ define fastcc void @caller_to0_from0() nounwind {
} }
define fastcc void @caller_to0_from8([8 x i32], i64) { define fastcc void @caller_to0_from8([8 x i32], i64) {
; CHECK: caller_to0_from8: ; CHECK-LABEL: caller_to0_from8:
tail call fastcc void @callee_stack0() tail call fastcc void @callee_stack0()
ret void ret void
@ -22,7 +22,7 @@ define fastcc void @caller_to0_from8([8 x i32], i64) {
} }
define fastcc void @caller_to8_from0() { define fastcc void @caller_to8_from0() {
; CHECK: caller_to8_from0: ; CHECK-LABEL: caller_to8_from0:
; CHECK: sub sp, sp, #32 ; CHECK: sub sp, sp, #32
; Key point is that the "42" should go #16 below incoming stack ; Key point is that the "42" should go #16 below incoming stack
@ -35,7 +35,7 @@ define fastcc void @caller_to8_from0() {
} }
define fastcc void @caller_to8_from8([8 x i32], i64 %a) { define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
; CHECK: caller_to8_from8: ; CHECK-LABEL: caller_to8_from8:
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at SP on entry. ; Key point is that the "%a" should go where at SP on entry.
@ -47,7 +47,7 @@ define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
} }
define fastcc void @caller_to16_from8([8 x i32], i64 %a) { define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
; CHECK: caller_to16_from8: ; CHECK-LABEL: caller_to16_from8:
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Important point is that the call reuses the "dead" argument space ; Important point is that the call reuses the "dead" argument space
@ -63,7 +63,7 @@ define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) { define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
; CHECK: caller_to8_from24: ; CHECK-LABEL: caller_to8_from24:
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at #16 above SP on entry. ; Key point is that the "%a" should go where at #16 above SP on entry.
@ -76,7 +76,7 @@ define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
; CHECK: caller_to16_from16: ; CHECK-LABEL: caller_to16_from16:
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Here we want to make sure that both loads happen before the stores: ; Here we want to make sure that both loads happen before the stores:

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@ -4,7 +4,7 @@
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
; CHECK: dct_luma_sp: ; CHECK-LABEL: dct_luma_sp:
define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
entry: entry:
; Make sure to use base-updating stores for saving callee-saved registers. ; Make sure to use base-updating stores for saving callee-saved registers.

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@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; pr4843 ; pr4843
define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind { define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
;CHECK: v2regbug: ;CHECK-LABEL: v2regbug:
;CHECK: vzip.16 ;CHECK: vzip.16
%tmp1 = load <4 x i16>* %B %tmp1 = load <4 x i16>* %B
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1> %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>

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@ -4,7 +4,7 @@
%0 = type { double, double } %0 = type { double, double }
define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK: bl __aeabi_dadd ; CHECK: bl __aeabi_dadd
; CHECK-NOT: strd ; CHECK-NOT: strd
; CHECK: mov ; CHECK: mov

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@ -12,7 +12,7 @@ entry:
%3 = fmul float %0, %1 ; <float> [#uses=1] %3 = fmul float %0, %1 ; <float> [#uses=1]
%4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1] %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
%5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1] %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00 ; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
%6 = fsub float 1.000000e+00, undef ; <float> [#uses=2] %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
%7 = fsub float %2, undef ; <float> [#uses=1] %7 = fsub float %2, undef ; <float> [#uses=1]

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@ -6,10 +6,10 @@
define zeroext i8 @t(%struct.foo* %this) noreturn optsize { define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
entry: entry:
; ARM: t: ; ARM-LABEL: t:
; ARM: str r2, [r1], r0 ; ARM: str r2, [r1], r0
; THUMB: t: ; THUMB-LABEL: t:
; THUMB-NOT: str r0, [r1], r0 ; THUMB-NOT: str r0, [r1], r0
; THUMB: str r1, [r0] ; THUMB: str r1, [r0]
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]

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@ -4,7 +4,7 @@
define i32* @t(i32* %x) nounwind { define i32* @t(i32* %x) nounwind {
entry: entry:
; ARM: t: ; ARM-LABEL: t:
; ARM: push ; ARM: push
; ARM: mov r7, sp ; ARM: mov r7, sp
; ARM: bl _foo ; ARM: bl _foo
@ -12,7 +12,7 @@ entry:
; ARM: bl _foo ; ARM: bl _foo
; ARM: pop {r7, pc} ; ARM: pop {r7, pc}
; THUMB2: t: ; THUMB2-LABEL: t:
; THUMB2: push ; THUMB2: push
; THUMB2: mov r7, sp ; THUMB2: mov r7, sp
; THUMB2: blx _foo ; THUMB2: blx _foo

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@ -3,7 +3,7 @@
define hidden void @foo() nounwind ssp { define hidden void @foo() nounwind ssp {
entry: entry:
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK: mov r7, sp ; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vpush {d10, d11} ; CHECK-NEXT: vpush {d10, d11}

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@ -9,7 +9,7 @@
@oStruct = external global %struct.Outer, align 4 @oStruct = external global %struct.Outer, align 4
define void @main() nounwind { define void @main() nounwind {
; CHECK: main: ; CHECK-LABEL: main:
; CHECK-NOT: ldrd ; CHECK-NOT: ldrd
; CHECK: mul ; CHECK: mul
for.body.lr.ph: for.body.lr.ph:

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@ -8,7 +8,7 @@
; rdar://9172742 ; rdar://9172742
define i32 @t() nounwind { define i32 @t() nounwind {
; CHECK: t: ; CHECK-LABEL: t:
entry: entry:
br label %bb2 br label %bb2

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@ -12,7 +12,7 @@ entry:
; Make sure the scheduler schedules all uses of the preincrement ; Make sure the scheduler schedules all uses of the preincrement
; induction variable before defining the postincrement value. ; induction variable before defining the postincrement value.
; CHECK: t: ; CHECK-LABEL: t:
; CHECK: %bb ; CHECK: %bb
; CHECK-NOT: mov ; CHECK-NOT: mov
bb: ; preds = %entry, %bb bb: ; preds = %entry, %bb

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@ -4,7 +4,7 @@
; rdar://9266679 ; rdar://9266679
define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
; CHECK: t: ; CHECK-LABEL: t:
entry: entry:
br label %for.cond br label %for.cond

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@ -10,7 +10,7 @@
@infoBlock = external global %struct.InformationBlock @infoBlock = external global %struct.InformationBlock
define hidden void @foo() { define hidden void @foo() {
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK: ldr.w ; CHECK: ldr.w
; CHECK: ldr.w ; CHECK: ldr.w
; CHECK-NOT: ldm ; CHECK-NOT: ldm

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@ -23,7 +23,7 @@
; ;
; rdar://11116189 ; rdar://11116189
define i64 @t(i64 %aInput) nounwind { define i64 @t(i64 %aInput) nounwind {
; CHECK: t: ; CHECK-LABEL: t:
; CHECK: movs [[REG:(r[0-9]+)]], #0 ; CHECK: movs [[REG:(r[0-9]+)]], #0
; CHECK: movt [[REG]], #46540 ; CHECK: movt [[REG]], #46540
; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]

View File

@ -13,7 +13,7 @@
; v4i8 ; v4i8
; ;
define void @sextload_v4i8_c(<4 x i8>* %v) nounwind { define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
;CHECK: sextload_v4i8_c: ;CHECK-LABEL: sextload_v4i8_c:
entry: entry:
%0 = load <4 x i8>* %v, align 8 %0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32> %v0 = sext <4 x i8> %0 to <4 x i32>
@ -26,7 +26,7 @@ entry:
; v2i8 ; v2i8
; ;
define void @sextload_v2i8_c(<2 x i8>* %v) nounwind { define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
;CHECK: sextload_v2i8_c: ;CHECK-LABEL: sextload_v2i8_c:
entry: entry:
%0 = load <2 x i8>* %v, align 8 %0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64> %v0 = sext <2 x i8> %0 to <2 x i64>
@ -39,7 +39,7 @@ entry:
; v2i16 ; v2i16
; ;
define void @sextload_v2i16_c(<2 x i16>* %v) nounwind { define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
;CHECK: sextload_v2i16_c: ;CHECK-LABEL: sextload_v2i16_c:
entry: entry:
%0 = load <2 x i16>* %v, align 8 %0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64> %v0 = sext <2 x i16> %0 to <2 x i64>
@ -54,7 +54,7 @@ entry:
; v4i8 ; v4i8
; ;
define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind { define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
;CHECK: sextload_v4i8_v: ;CHECK-LABEL: sextload_v4i8_v:
entry: entry:
%0 = load <4 x i8>* %v, align 8 %0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32> %v0 = sext <4 x i8> %0 to <4 x i32>
@ -70,7 +70,7 @@ entry:
; v2i8 ; v2i8
; ;
define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind { define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
;CHECK: sextload_v2i8_v: ;CHECK-LABEL: sextload_v2i8_v:
entry: entry:
%0 = load <2 x i8>* %v, align 8 %0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64> %v0 = sext <2 x i8> %0 to <2 x i64>
@ -86,7 +86,7 @@ entry:
; v2i16 ; v2i16
; ;
define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind { define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
;CHECK: sextload_v2i16_v: ;CHECK-LABEL: sextload_v2i16_v:
entry: entry:
%0 = load <2 x i16>* %v, align 8 %0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64> %v0 = sext <2 x i16> %0 to <2 x i64>
@ -104,7 +104,7 @@ entry:
; v4i8 x v4i16 ; v4i8 x v4i16
; ;
define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind { define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
;CHECK: sextload_v4i8_vs: ;CHECK-LABEL: sextload_v4i8_vs:
entry: entry:
%0 = load <4 x i8>* %v, align 8 %0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32> %v0 = sext <4 x i8> %0 to <4 x i32>
@ -120,7 +120,7 @@ entry:
; v2i8 ; v2i8
; v2i8 x v2i16 ; v2i8 x v2i16
define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind { define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
;CHECK: sextload_v2i8_vs: ;CHECK-LABEL: sextload_v2i8_vs:
entry: entry:
%0 = load <2 x i8>* %v, align 8 %0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64> %v0 = sext <2 x i8> %0 to <2 x i64>
@ -136,7 +136,7 @@ entry:
; v2i16 ; v2i16
; v2i16 x v2i32 ; v2i16 x v2i32
define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind { define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
;CHECK: sextload_v2i16_vs: ;CHECK-LABEL: sextload_v2i16_vs:
entry: entry:
%0 = load <2 x i16>* %v, align 8 %0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64> %v0 = sext <2 x i16> %0 to <2 x i64>

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@ -4,7 +4,7 @@
; rdar://12300648 ; rdar://12300648
define i32 @t(i32 %x) { define i32 @t(i32 %x) {
; CHECK: t: ; CHECK-LABEL: t:
; CHECK-NOT: movw ; CHECK-NOT: movw
%tmp = add i32 %x, -65535 %tmp = add i32 %x, -65535
ret i32 %tmp ret i32 %tmp

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@ -23,7 +23,7 @@ entry:
ret void ret void
} }
; CHECK: main: ; CHECK-LABEL: main:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val ; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything. ; ldm is not formed when the coalescer failed to coalesce everything.
@ -53,7 +53,7 @@ entry:
ret void ret void
} }
; CHECK: main_fixed_arg: ; CHECK-LABEL: main_fixed_arg:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val ; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything. ; ldm is not formed when the coalescer failed to coalesce everything.

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@ -6,7 +6,7 @@
declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val); declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
; CHECK: main: ; CHECK-LABEL: main:
define i32 @main() nounwind { define i32 @main() nounwind {
entry: entry:
; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1 ; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1

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@ -5,7 +5,7 @@
declare void @f(%struct.s* %p); declare void @f(%struct.s* %p);
; CHECK: t: ; CHECK-LABEL: t:
define void @t(i32 %a, %struct.s* byval %s) nounwind { define void @t(i32 %a, %struct.s* byval %s) nounwind {
entry: entry:
@ -20,7 +20,7 @@ entry:
ret void ret void
} }
; CHECK: caller: ; CHECK-LABEL: caller:
define void @caller() { define void @caller() {
; CHECK: ldm r0, {r1, r2, r3} ; CHECK: ldm r0, {r1, r2, r3}

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@ -2,8 +2,8 @@
;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s ;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
;EXPECTED: foo: ;EXPECTED-LABEL: foo:
;CHECK: foo: ;CHECK-LABEL: foo:
define i32 @foo(i32* %a) nounwind optsize { define i32 @foo(i32* %a) nounwind optsize {
entry: entry:
%0 = load i32* %a, align 4 %0 = load i32* %a, align 4

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@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4 ; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind { define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
; CHECK: muladd: ; CHECK-LABEL: muladd:
; CHECK: fmaf ; CHECK: fmaf
; CHECK: fmaf ; CHECK: fmaf
; CHECK: fmaf ; CHECK: fmaf
@ -17,7 +17,7 @@ define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounw
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind { define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
; CHECK: muladd2: ; CHECK-LABEL: muladd2:
; CHECK: fmaf ; CHECK: fmaf
; CHECK: fmaf ; CHECK: fmaf
; CHECK-NOT: fmaf ; CHECK-NOT: fmaf

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@ -1,7 +1,7 @@
;PR15293: ARM codegen ice - expected larger existing stack allocation ;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
;CHECK: foo: ;CHECK-LABEL: foo:
;CHECK: sub sp, sp, #8 ;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8] ;CHECK: str r0, [sp, #8]
@ -11,7 +11,7 @@
;CHECK: add sp, sp, #8 ;CHECK: add sp, sp, #8
;CHECK: mov pc, lr ;CHECK: mov pc, lr
;CHECK: foo2: ;CHECK-LABEL: foo2:
;CHECK: sub sp, sp, #8 ;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8] ;CHECK: str r0, [sp, #8]
@ -24,7 +24,7 @@
;CHECK: add sp, sp, #8 ;CHECK: add sp, sp, #8
;CHECK: mov pc, lr ;CHECK: mov pc, lr
;CHECK: doFoo: ;CHECK-LABEL: doFoo:
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: ldr r0, ;CHECK: ldr r0,
;CHECK: ldr r0, [r0] ;CHECK: ldr r0, [r0]
@ -33,7 +33,7 @@
;CHECK: mov pc, lr ;CHECK: mov pc, lr
;CHECK: doFoo2: ;CHECK-LABEL: doFoo2:
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: ldr r0, ;CHECK: ldr r0,
;CHECK: mov r1, #0 ;CHECK: mov r1, #0

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@ -53,11 +53,11 @@
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
; ;
;CHECK: foo: ;CHECK-LABEL: foo:
;CHECK-NOT: mov r0 ;CHECK-NOT: mov r0
;CHECK-NOT: ldr r0 ;CHECK-NOT: ldr r0
;CHECK: bl fooUseI32 ;CHECK: bl fooUseI32
;CHECK: doFoo: ;CHECK-LABEL: doFoo:
;CHECK: movs r0, #43 ;CHECK: movs r0, #43
;CHECK: bl foo ;CHECK: bl foo

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@ -9,7 +9,7 @@
@.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1 @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
;CHECK: printfn: ;CHECK-LABEL: printfn:
define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
entry: entry:
%conv = sext i16 %b to i32 %conv = sext i16 %b to i32

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@ -2,7 +2,7 @@
; rdar://13782395 ; rdar://13782395
define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
; CHECK: t1: ; CHECK-LABEL: t1:
; CHECK: Block address taken ; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen ; CHECK-NOT: Address of block that was removed by CodeGen
store i8* blockaddress(@t1, %cond_true), i8** %retaddr store i8* blockaddress(@t1, %cond_true), i8** %retaddr
@ -19,7 +19,7 @@ cond_false:
} }
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) { define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
; CHECK: t2: ; CHECK-LABEL: t2:
; CHECK: Block address taken ; CHECK: Block address taken
; CHECK: %cond_true ; CHECK: %cond_true
; CHECK: add ; CHECK: add
@ -41,7 +41,7 @@ UnifiedReturnBlock:
} }
define hidden fastcc void @t3(i8** %retaddr) { define hidden fastcc void @t3(i8** %retaddr) {
; CHECK: t3: ; CHECK-LABEL: t3:
; CHECK: Block address taken ; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen ; CHECK-NOT: Address of block that was removed by CodeGen
bb: bb:

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@ -1,8 +1,8 @@
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
; CHECK-ENABLED: t1: ; CHECK-ENABLED-LABEL: t1:
; CHECK-DISABLED: t1: ; CHECK-DISABLED-LABEL: t1:
define <2 x float> @t1(float %f) { define <2 x float> @t1(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@ -11,8 +11,8 @@ define <2 x float> @t1(float %f) {
ret <2 x float> %i2 ret <2 x float> %i2
} }
; CHECK-ENABLED: t2: ; CHECK-ENABLED-LABEL: t2:
; CHECK-DISABLED: t2: ; CHECK-DISABLED-LABEL: t2:
define <4 x float> @t2(float %g, float %f) { define <4 x float> @t2(float %g, float %f) {
; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0] ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@ -21,8 +21,8 @@ define <4 x float> @t2(float %g, float %f) {
ret <4 x float> %i2 ret <4 x float> %i2
} }
; CHECK-ENABLED: t3: ; CHECK-ENABLED-LABEL: t3:
; CHECK-DISABLED: t3: ; CHECK-DISABLED-LABEL: t3:
define arm_aapcs_vfpcc <2 x float> @t3(float %f) { define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@ -31,8 +31,8 @@ define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
ret <2 x float> %i2 ret <2 x float> %i2
} }
; CHECK-ENABLED: t4: ; CHECK-ENABLED-LABEL: t4:
; CHECK-DISABLED: t4: ; CHECK-DISABLED-LABEL: t4:
define <2 x float> @t4(float %f) { define <2 x float> @t4(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup ; CHECK-DISABLED-NOT: vdup
@ -45,8 +45,8 @@ b:
ret <2 x float> %i2 ret <2 x float> %i2
} }
; CHECK-ENABLED: t5: ; CHECK-ENABLED-LABEL: t5:
; CHECK-DISABLED: t5: ; CHECK-DISABLED-LABEL: t5:
define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) { define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
; CHECK-ENABLED: vadd.f32 ; CHECK-ENABLED: vadd.f32

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@ -1,6 +1,6 @@
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
; CHECK: t1: ; CHECK-LABEL: t1:
define <2 x float> @t1(float* %A, <2 x float> %B) { define <2 x float> @t1(float* %A, <2 x float> %B) {
; The generated code for this test uses a vld1.32 instruction ; The generated code for this test uses a vld1.32 instruction
; to write the lane 1 of a D register containing the value of ; to write the lane 1 of a D register containing the value of
@ -15,7 +15,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) {
ret <2 x float> %tmp3 ret <2 x float> %tmp3
} }
; CHECK: t2: ; CHECK-LABEL: t2:
define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) { define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
entry: entry:
br label %loop br label %loop

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@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
define i32 @f1(i32 %a, i64 %b) { define i32 @f1(i32 %a, i64 %b) {
; ELF: f1: ; ELF-LABEL: f1:
; ELF: mov r0, r2 ; ELF: mov r0, r2
; DARWIN: f1: ; DARWIN-LABEL: f1:
; DARWIN: mov r0, r1 ; DARWIN: mov r0, r1
%tmp = call i32 @g1(i64 %b) %tmp = call i32 @g1(i64 %b)
ret i32 %tmp ret i32 %tmp
@ -12,10 +12,10 @@ define i32 @f1(i32 %a, i64 %b) {
; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi. ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
define i32 @f2() nounwind optsize { define i32 @f2() nounwind optsize {
; ELF: f2: ; ELF-LABEL: f2:
; ELF: mov [[REGISTER:(r[0-9]+)]], #128 ; ELF: mov [[REGISTER:(r[0-9]+)]], #128
; ELF: str [[REGISTER]], [ ; ELF: str [[REGISTER]], [
; DARWIN: f2: ; DARWIN-LABEL: f2:
; DARWIN: mov r3, #128 ; DARWIN: mov r3, #128
entry: entry:
%0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1] %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
@ -26,10 +26,10 @@ entry:
; test that on gnueabi a 64 bit value at this position will cause r3 to go ; test that on gnueabi a 64 bit value at this position will cause r3 to go
; unused and the value stored in [sp] ; unused and the value stored in [sp]
; ELF: f3: ; ELF-LABEL: f3:
; ELF: ldr r0, [sp] ; ELF: ldr r0, [sp]
; ELF-NEXT: mov pc, lr ; ELF-NEXT: mov pc, lr
; DARWIN: f3: ; DARWIN-LABEL: f3:
; DARWIN: mov r0, r3 ; DARWIN: mov r0, r3
; DARWIN-NEXT: mov pc, lr ; DARWIN-NEXT: mov pc, lr
define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) { define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {

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@ -5,10 +5,10 @@
define i8* @t() nounwind { define i8* @t() nounwind {
entry: entry:
; DARWIN: t: ; DARWIN-LABEL: t:
; DARWIN: mov r0, r7 ; DARWIN: mov r0, r7
; LINUX: t: ; LINUX-LABEL: t:
; LINUX: mov r0, r11 ; LINUX: mov r0, r11
%0 = call i8* @llvm.frameaddress(i32 0) %0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0 ret i8* %0

View File

@ -7,7 +7,7 @@
define i8* @rt0(i32 %x) nounwind readnone { define i8* @rt0(i32 %x) nounwind readnone {
entry: entry:
; CHECK: rt0: ; CHECK-LABEL: rt0:
; CHECK: {r7, lr} ; CHECK: {r7, lr}
; CHECK: mov r0, lr ; CHECK: mov r0, lr
%0 = tail call i8* @llvm.returnaddress(i32 0) %0 = tail call i8* @llvm.returnaddress(i32 0)
@ -16,7 +16,7 @@ entry:
define i8* @rt2() nounwind readnone { define i8* @rt2() nounwind readnone {
entry: entry:
; CHECK: rt2: ; CHECK-LABEL: rt2:
; CHECK: {r7, lr} ; CHECK: {r7, lr}
; CHECK: ldr r[[R0:[0-9]+]], [r7] ; CHECK: ldr r[[R0:[0-9]+]], [r7]
; CHECK: ldr r0, [r0] ; CHECK: ldr r0, [r0]

View File

@ -12,7 +12,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test1: ; CHECK-THUMB-LABEL: test1:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]] ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
@ -37,7 +37,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test2: ; CHECK-THUMB-LABEL: test2:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]] ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
@ -62,7 +62,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test3: ; CHECK-THUMB-LABEL: test3:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]] ; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
@ -87,7 +87,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test4: ; CHECK-THUMB-LABEL: test4:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]] ; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
@ -112,7 +112,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test5: ; CHECK-THUMB-LABEL: test5:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]] ; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
@ -135,7 +135,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test6: ; CHECK-THUMB-LABEL: test6:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@ -159,7 +159,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test7: ; CHECK-THUMB-LABEL: test7:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]] ; CHECK-THUMB: cmp [[REG1]]
@ -188,7 +188,7 @@ define i64 @test8(i64* %ptr) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test8: ; CHECK-THUMB-LABEL: test8:
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]] ; CHECK-THUMB: cmp [[REG1]]
; CHECK-THUMB: it eq ; CHECK-THUMB: it eq
@ -214,7 +214,7 @@ define void @test9(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test9: ; CHECK-THUMB-LABEL: test9:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
@ -238,7 +238,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test10: ; CHECK-THUMB-LABEL: test10:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@ -266,7 +266,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test11: ; CHECK-THUMB-LABEL: test11:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@ -293,7 +293,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test12: ; CHECK-THUMB-LABEL: test12:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
@ -320,7 +320,7 @@ define i64 @test13(i64* %ptr, i64 %val) {
; CHECK: bne ; CHECK: bne
; CHECK: dmb {{ish$}} ; CHECK: dmb {{ish$}}
; CHECK-THUMB: test13: ; CHECK-THUMB-LABEL: test13:
; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]

View File

@ -3,11 +3,11 @@
; rdar://8964854 ; rdar://8964854
define i8 @t(i8* %a, i8 %b, i8 %c) nounwind { define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
; ARM: t: ; ARM-LABEL: t:
; ARM: ldrexb ; ARM: ldrexb
; ARM: strexb ; ARM: strexb
; T2: t: ; T2-LABEL: t:
; T2: ldrexb ; T2: ldrexb
; T2: strexb ; T2: strexb
%tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic

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@ -1,6 +1,6 @@
; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
; CHECK: max: ; CHECK-LABEL: max:
define i32 @max(i8 %ctx, i32* %ptr, i32 %val) define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
{ {
; CHECK: ldrex ; CHECK: ldrex
@ -10,7 +10,7 @@ define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
ret i32 %old ret i32 %old
} }
; CHECK: min: ; CHECK-LABEL: min:
define i32 @min(i8 %ctx, i32* %ptr, i32 %val) define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
{ {
; CHECK: ldrex ; CHECK: ldrex

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@ -6,7 +6,7 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry: entry:
; CHECK: t1: ; CHECK-LABEL: t1:
; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
; CHECK-NEXT: muls r0, [[REG]], [[REG2]] ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
; rdar://10357570 ; rdar://10357570
define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
entry: entry:
; CHECK: t2: ; CHECK-LABEL: t2:
%tobool7 = icmp eq i32* %ptr2, null %tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body br i1 %tobool7, label %while.end, label %while.body
@ -54,7 +54,7 @@ while.end:
; rdar://12878928 ; rdar://12878928
define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
entry: entry:
; CHECK: t3: ; CHECK-LABEL: t3:
%tobool7 = icmp eq i32* %ptr2, null %tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body br i1 %tobool7, label %while.end, label %while.body

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@ -2,7 +2,7 @@
; 4278190095 = 0xff00000f ; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK: f1: ; CHECK-LABEL: f1:
; CHECK: bfc ; CHECK: bfc
%tmp = and i32 %a, 4278190095 %tmp = and i32 %a, 4278190095
ret i32 %tmp ret i32 %tmp
@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
; 4286578688 = 0xff800000 ; 4286578688 = 0xff800000
define i32 @f2(i32 %a) { define i32 @f2(i32 %a) {
; CHECK: f2: ; CHECK-LABEL: f2:
; CHECK: bfc ; CHECK: bfc
%tmp = and i32 %a, 4286578688 %tmp = and i32 %a, 4286578688
ret i32 %tmp ret i32 %tmp
@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
; 4095 = 0x00000fff ; 4095 = 0x00000fff
define i32 @f3(i32 %a) { define i32 @f3(i32 %a) {
; CHECK: f3: ; CHECK-LABEL: f3:
; CHECK: bfc ; CHECK: bfc
%tmp = and i32 %a, 4095 %tmp = and i32 %a, 4095
ret i32 %tmp ret i32 %tmp

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@ -52,7 +52,7 @@ define i32 @f4(i32 %a) nounwind {
; rdar://8458663 ; rdar://8458663
define i32 @f5(i32 %a, i32 %b) nounwind { define i32 @f5(i32 %a, i32 %b) nounwind {
entry: entry:
; CHECK: f5: ; CHECK-LABEL: f5:
; CHECK-NOT: bfc ; CHECK-NOT: bfc
; CHECK: bfi r0, r1, #20, #4 ; CHECK: bfi r0, r1, #20, #4
%0 = and i32 %a, -15728641 %0 = and i32 %a, -15728641
@ -65,7 +65,7 @@ entry:
; rdar://9609030 ; rdar://9609030
define i32 @f6(i32 %a, i32 %b) nounwind readnone { define i32 @f6(i32 %a, i32 %b) nounwind readnone {
entry: entry:
; CHECK: f6: ; CHECK-LABEL: f6:
; CHECK-NOT: bic ; CHECK-NOT: bic
; CHECK: bfi r0, r1, #8, #9 ; CHECK: bfi r0, r1, #8, #9
%and = and i32 %a, -130817 %and = and i32 %a, -130817

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@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
define i32 @t1(i32 %x) nounwind { define i32 @t1(i32 %x) nounwind {
; CHECK: t1: ; CHECK-LABEL: t1:
; CHECK-NOT: InlineAsm ; CHECK-NOT: InlineAsm
; CHECK: rev ; CHECK: rev
%asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind

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@ -4,10 +4,10 @@
define void @t1() noreturn minsize nounwind ssp { define void @t1() noreturn minsize nounwind ssp {
entry: entry:
; ARM: t1: ; ARM-LABEL: t1:
; ARM: bl _bar ; ARM: bl _bar
; SWIFT: t1: ; SWIFT-LABEL: t1:
; SWIFT: bl _bar ; SWIFT: bl _bar
tail call void @bar() noreturn nounwind tail call void @bar() noreturn nounwind
unreachable unreachable
@ -15,10 +15,10 @@ entry:
define void @t2() noreturn minsize nounwind ssp { define void @t2() noreturn minsize nounwind ssp {
entry: entry:
; ARM: t2: ; ARM-LABEL: t2:
; ARM: bl _t1 ; ARM: bl _t1
; SWIFT: t2: ; SWIFT-LABEL: t2:
; SWIFT: bl _t1 ; SWIFT: bl _t1
tail call void @t1() noreturn nounwind tail call void @t1() noreturn nounwind
unreachable unreachable

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@ -4,11 +4,11 @@
define void @t1() noreturn nounwind ssp { define void @t1() noreturn nounwind ssp {
entry: entry:
; ARM: t1: ; ARM-LABEL: t1:
; ARM: mov lr, pc ; ARM: mov lr, pc
; ARM: b _bar ; ARM: b _bar
; SWIFT: t1: ; SWIFT-LABEL: t1:
; SWIFT: mov lr, pc ; SWIFT: mov lr, pc
; SWIFT: b _bar ; SWIFT: b _bar
tail call void @bar() noreturn nounwind tail call void @bar() noreturn nounwind
@ -17,11 +17,11 @@ entry:
define void @t2() noreturn nounwind ssp { define void @t2() noreturn nounwind ssp {
entry: entry:
; ARM: t2: ; ARM-LABEL: t2:
; ARM: mov lr, pc ; ARM: mov lr, pc
; ARM: b _t1 ; ARM: b _t1
; SWIFT: t2: ; SWIFT-LABEL: t2:
; SWIFT: mov lr, pc ; SWIFT: mov lr, pc
; SWIFT: b _t1 ; SWIFT: b _t1
tail call void @t1() noreturn nounwind tail call void @t1() noreturn nounwind

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@ -11,16 +11,16 @@
declare void @g(i32, i32, i32, i32) declare void @g(i32, i32, i32, i32)
define void @t1() { define void @t1() {
; CHECKELF: t1: ; CHECKELF-LABEL: t1:
; CHECKELF: bl g(PLT) ; CHECKELF: bl g(PLT)
call void @g( i32 1, i32 2, i32 3, i32 4 ) call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void ret void
} }
define void @t2() { define void @t2() {
; CHECKV6: t2: ; CHECKV6-LABEL: t2:
; CHECKV6: bx r0 ; CHECKV6: bx r0
; CHECKT2D: t2: ; CHECKT2D-LABEL: t2:
; CHECKT2D: ldr ; CHECKT2D: ldr
; CHECKT2D-NEXT: ldr ; CHECKT2D-NEXT: ldr
; CHECKT2D-NEXT: bx r0 ; CHECKT2D-NEXT: bx r0
@ -30,11 +30,11 @@ define void @t2() {
} }
define void @t3() { define void @t3() {
; CHECKV6: t3: ; CHECKV6-LABEL: t3:
; CHECKV6: b _t2 ; CHECKV6: b _t2
; CHECKELF: t3: ; CHECKELF-LABEL: t3:
; CHECKELF: b t2(PLT) ; CHECKELF: b t2(PLT)
; CHECKT2D: t3: ; CHECKT2D-LABEL: t3:
; CHECKT2D: b.w _t2 ; CHECKT2D: b.w _t2
tail call void @t2( ) ; <i32> [#uses=0] tail call void @t2( ) ; <i32> [#uses=0]
@ -44,9 +44,9 @@ define void @t3() {
; Sibcall optimization of expanded libcalls. rdar://8707777 ; Sibcall optimization of expanded libcalls. rdar://8707777
define double @t4(double %a) nounwind readonly ssp { define double @t4(double %a) nounwind readonly ssp {
entry: entry:
; CHECKV6: t4: ; CHECKV6-LABEL: t4:
; CHECKV6: b _sin ; CHECKV6: b _sin
; CHECKELF: t4: ; CHECKELF-LABEL: t4:
; CHECKELF: b sin(PLT) ; CHECKELF: b sin(PLT)
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1] %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0 ret double %0
@ -54,9 +54,9 @@ entry:
define float @t5(float %a) nounwind readonly ssp { define float @t5(float %a) nounwind readonly ssp {
entry: entry:
; CHECKV6: t5: ; CHECKV6-LABEL: t5:
; CHECKV6: b _sinf ; CHECKV6: b _sinf
; CHECKELF: t5: ; CHECKELF-LABEL: t5:
; CHECKELF: b sinf(PLT) ; CHECKELF: b sinf(PLT)
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1] %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0 ret float %0
@ -68,9 +68,9 @@ declare double @sin(double) nounwind readonly
define i32 @t6(i32 %a, i32 %b) nounwind readnone { define i32 @t6(i32 %a, i32 %b) nounwind readnone {
entry: entry:
; CHECKV6: t6: ; CHECKV6-LABEL: t6:
; CHECKV6: b ___divsi3 ; CHECKV6: b ___divsi3
; CHECKELF: t6: ; CHECKELF-LABEL: t6:
; CHECKELF: b __aeabi_idiv(PLT) ; CHECKELF: b __aeabi_idiv(PLT)
%0 = sdiv i32 %a, %b %0 = sdiv i32 %a, %b
ret i32 %0 ret i32 %0
@ -82,7 +82,7 @@ declare void @foo() nounwind
define void @t7() nounwind { define void @t7() nounwind {
entry: entry:
; CHECKT2D: t7: ; CHECKT2D-LABEL: t7:
; CHECKT2D: blxeq _foo ; CHECKT2D: blxeq _foo
; CHECKT2D-NEXT: pop.w ; CHECKT2D-NEXT: pop.w
; CHECKT2D-NEXT: b.w _foo ; CHECKT2D-NEXT: b.w _foo
@ -101,7 +101,7 @@ bb:
; rdar://11140249 ; rdar://11140249
define i32 @t8(i32 %x) nounwind ssp { define i32 @t8(i32 %x) nounwind ssp {
entry: entry:
; CHECKT2D: t8: ; CHECKT2D-LABEL: t8:
; CHECKT2D-NOT: push ; CHECKT2D-NOT: push
%and = and i32 %x, 1 %and = and i32 %x, 1
%tobool = icmp eq i32 %and, 0 %tobool = icmp eq i32 %and, 0
@ -147,7 +147,7 @@ declare i32 @c(i32)
@x = external global i32, align 4 @x = external global i32, align 4
define i32 @t9() nounwind { define i32 @t9() nounwind {
; CHECKT2D: t9: ; CHECKT2D-LABEL: t9:
; CHECKT2D: blx __ZN9MutexLockC1Ev ; CHECKT2D: blx __ZN9MutexLockC1Ev
; CHECKT2D: blx __ZN9MutexLockD1Ev ; CHECKT2D: blx __ZN9MutexLockD1Ev
; CHECKT2D: b.w ___divsi3 ; CHECKT2D: b.w ___divsi3
@ -167,7 +167,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou
; Correctly preserve the input chain for the tailcall node in the bitcast case, ; Correctly preserve the input chain for the tailcall node in the bitcast case,
; otherwise the call to floorf is lost. ; otherwise the call to floorf is lost.
define float @libcall_tc_test2(float* nocapture %a, float %b) { define float @libcall_tc_test2(float* nocapture %a, float %b) {
; CHECKT2D: libcall_tc_test2: ; CHECKT2D-LABEL: libcall_tc_test2:
; CHECKT2D: blx _floorf ; CHECKT2D: blx _floorf
; CHECKT2D: b.w _truncf ; CHECKT2D: b.w _truncf
%1 = load float* %a, align 4 %1 = load float* %a, align 4

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@ -7,7 +7,7 @@
@numi = external global i32 ; <i32*> [#uses=1] @numi = external global i32 ; <i32*> [#uses=1]
@counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1] @counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i: ; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
; CHECK-NOT: bx lr ; CHECK-NOT: bx lr
define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() { define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
@ -56,7 +56,7 @@ define void @PR15520(void ()* %fn) {
call void %fn() call void %fn()
ret void ret void
; CHECK: PR15520: ; CHECK-LABEL: PR15520:
; CHECK: mov lr, pc ; CHECK: mov lr, pc
; CHECK: mov pc, r0 ; CHECK: mov pc, r0
} }

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@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm | FileCheck %s ; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1(i64 %a, i64 %b) { define i64 @f1(i64 %a, i64 %b) {
; CHECK: f1: ; CHECK-LABEL: f1:
; CHECK: subs r ; CHECK: subs r
; CHECK: sbc r ; CHECK: sbc r
entry: entry:
@ -10,7 +10,7 @@ entry:
} }
define i64 @f2(i64 %a, i64 %b) { define i64 @f2(i64 %a, i64 %b) {
; CHECK: f2: ; CHECK-LABEL: f2:
; CHECK: adc r ; CHECK: adc r
; CHECK: subs r ; CHECK: subs r
; CHECK: sbc r ; CHECK: sbc r
@ -22,7 +22,7 @@ entry:
; add with live carry ; add with live carry
define i64 @f3(i32 %al, i32 %bl) { define i64 @f3(i32 %al, i32 %bl) {
; CHECK: f3: ; CHECK-LABEL: f3:
; CHECK: adds r ; CHECK: adds r
; CHECK: adc r ; CHECK: adc r
entry: entry:
@ -39,7 +39,7 @@ entry:
; rdar://10073745 ; rdar://10073745
define i64 @f4(i64 %x) nounwind readnone { define i64 @f4(i64 %x) nounwind readnone {
entry: entry:
; CHECK: f4: ; CHECK-LABEL: f4:
; CHECK: rsbs r ; CHECK: rsbs r
; CHECK: rsc r ; CHECK: rsc r
%0 = sub nsw i64 0, %x %0 = sub nsw i64 0, %x
@ -49,7 +49,7 @@ entry:
; rdar://12559385 ; rdar://12559385
define i64 @f5(i32 %vi) { define i64 @f5(i32 %vi) {
entry: entry:
; CHECK: f5: ; CHECK-LABEL: f5:
; CHECK: movw [[REG:r[0-9]+]], #36102 ; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64 %v0 = zext i32 %vi to i64

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@ -7,7 +7,7 @@
define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind { define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
entry: entry:
; CHECK: t1: ; CHECK-LABEL: t1:
%0 = icmp eq %struct.list_head* %list, null %0 = icmp eq %struct.list_head* %list, null
br i1 %0, label %bb2, label %bb br i1 %0, label %bb2, label %bb
@ -33,7 +33,7 @@ bb2:
; rdar://8117827 ; rdar://8117827
define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly { define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
entry: entry:
; CHECK: t2: ; CHECK-LABEL: t2:
; CHECK: beq LBB1_[[RET:.]] ; CHECK: beq LBB1_[[RET:.]]
%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1] %0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb.nph15 br i1 %0, label %bb5, label %bb.nph15

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@ -3,7 +3,7 @@
declare i32 @llvm.cttz.i32(i32, i1) declare i32 @llvm.cttz.i32(i32, i1)
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK: f1: ; CHECK-LABEL: f1:
; CHECK: rbit ; CHECK: rbit
; CHECK: clz ; CHECK: clz
%tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true ) %tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )

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@ -1,6 +1,6 @@
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
; CHECK: f: ; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) { define float @f(<4 x i16>* nocapture %in) {
; CHECK: vldr ; CHECK: vldr
; CHECK: vmovl.u16 ; CHECK: vmovl.u16

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@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
define double @f1() nounwind { define double @f1() nounwind {
; CHECK: f1: ; CHECK-LABEL: f1:
; CHECK: .data_region ; CHECK: .data_region
; CHECK: .long 1413754129 ; CHECK: .long 1413754129
; CHECK: .long 1074340347 ; CHECK: .long 1074340347
@ -11,7 +11,7 @@ define double @f1() nounwind {
define i32 @f2() { define i32 @f2() {
; CHECK: f2: ; CHECK-LABEL: f2:
; CHECK: .data_region jt32 ; CHECK: .data_region jt32
; CHECK: .end_data_region ; CHECK: .end_data_region

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@ -5,11 +5,11 @@
define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry: entry:
; A8: foo: ; A8-LABEL: foo:
; A8: bl ___divmodsi4 ; A8: bl ___divmodsi4
; A8-NOT: bl ___divmodsi4 ; A8-NOT: bl ___divmodsi4
; SWIFT: foo: ; SWIFT-LABEL: foo:
; SWIFT: sdiv ; SWIFT: sdiv
; SWIFT: mls ; SWIFT: mls
; SWIFT-NOT: bl __divmodsi4 ; SWIFT-NOT: bl __divmodsi4
@ -23,11 +23,11 @@ entry:
define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry: entry:
; A8: bar: ; A8-LABEL: bar:
; A8: bl ___udivmodsi4 ; A8: bl ___udivmodsi4
; A8-NOT: bl ___udivmodsi4 ; A8-NOT: bl ___udivmodsi4
; SWIFT: bar: ; SWIFT-LABEL: bar:
; SWIFT: udiv ; SWIFT: udiv
; SWIFT: mls ; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4 ; SWIFT-NOT: bl __udivmodsi4
@ -45,8 +45,8 @@ entry:
define void @do_indent(i32 %cols) nounwind { define void @do_indent(i32 %cols) nounwind {
entry: entry:
; A8: do_indent: ; A8-LABEL: do_indent:
; SWIFT: do_indent: ; SWIFT-LABEL: do_indent:
%0 = load i32* @flags, align 4 %0 = load i32* @flags, align 4
%1 = and i32 %0, 67108864 %1 = and i32 %0, 67108864
%2 = icmp eq i32 %1, 0 %2 = icmp eq i32 %1, 0
@ -77,11 +77,11 @@ declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
; rdar://11714607 ; rdar://11714607
define i32 @howmany(i32 %x, i32 %y) nounwind { define i32 @howmany(i32 %x, i32 %y) nounwind {
entry: entry:
; A8: howmany: ; A8-LABEL: howmany:
; A8: bl ___udivmodsi4 ; A8: bl ___udivmodsi4
; A8-NOT: ___udivsi3 ; A8-NOT: ___udivsi3
; SWIFT: howmany: ; SWIFT-LABEL: howmany:
; SWIFT: udiv ; SWIFT: udiv
; SWIFT: mls ; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4 ; SWIFT-NOT: bl __udivmodsi4

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@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*)
declare void @__cxa_call_unexpected(i8*) declare void @__cxa_call_unexpected(i8*)
define i32 @main() { define i32 @main() {
; CHECK: main: ; CHECK-LABEL: main:
entry: entry:
%exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
%0 = bitcast i8* %exception.i to i32* %0 = bitcast i8* %exception.i to i32*

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@ -112,7 +112,7 @@ declare void @__cxa_end_catch()
declare void @_ZSt9terminatev() declare void @_ZSt9terminatev()
; CHECK-FP: _Z4testiiiiiddddd: ; CHECK-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@ -124,7 +124,7 @@ declare void @_ZSt9terminatev()
; CHECK-FP: .handlerdata ; CHECK-FP: .handlerdata
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM: _Z4testiiiiiddddd: ; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@ -134,7 +134,7 @@ declare void @_ZSt9terminatev()
; CHECK-FP-ELIM: .handlerdata ; CHECK-FP-ELIM: .handlerdata
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP: _Z4testiiiiiddddd: ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r11, lr} ; CHECK-V7-FP: .save {r4, r11, lr}
; CHECK-V7-FP: push {r4, r11, lr} ; CHECK-V7-FP: push {r4, r11, lr}
@ -148,7 +148,7 @@ declare void @_ZSt9terminatev()
; CHECK-V7-FP: .handlerdata ; CHECK-V7-FP: .handlerdata
; CHECK-V7-FP: .fnend ; CHECK-V7-FP: .fnend
; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd: ; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, lr} ; CHECK-V7-FP-ELIM: .save {r4, lr}
; CHECK-V7-FP-ELIM: push {r4, lr} ; CHECK-V7-FP-ELIM: push {r4, lr}
@ -173,7 +173,7 @@ entry:
ret void ret void
} }
; CHECK-FP: test2: ; CHECK-FP-LABEL: test2:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: .save {r11, lr} ; CHECK-FP: .save {r11, lr}
; CHECK-FP: push {r11, lr} ; CHECK-FP: push {r11, lr}
@ -183,7 +183,7 @@ entry:
; CHECK-FP: mov pc, lr ; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM: test2: ; CHECK-FP-ELIM-LABEL: test2:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r11, lr} ; CHECK-FP-ELIM: .save {r11, lr}
; CHECK-FP-ELIM: push {r11, lr} ; CHECK-FP-ELIM: push {r11, lr}
@ -191,7 +191,7 @@ entry:
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP: test2: ; CHECK-V7-FP-LABEL: test2:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r11, lr} ; CHECK-V7-FP: .save {r11, lr}
; CHECK-V7-FP: push {r11, lr} ; CHECK-V7-FP: push {r11, lr}
@ -200,7 +200,7 @@ entry:
; CHECK-V7-FP: pop {r11, pc} ; CHECK-V7-FP: pop {r11, pc}
; CHECK-V7-FP: .fnend ; CHECK-V7-FP: .fnend
; CHECK-V7-FP-ELIM: test2: ; CHECK-V7-FP-ELIM-LABEL: test2:
; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r11, lr} ; CHECK-V7-FP-ELIM: .save {r11, lr}
; CHECK-V7-FP-ELIM: push {r11, lr} ; CHECK-V7-FP-ELIM: push {r11, lr}
@ -229,7 +229,7 @@ entry:
ret i32 %add6 ret i32 %add6
} }
; CHECK-FP: test3: ; CHECK-FP-LABEL: test3:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r11, lr} ; CHECK-FP: .save {r4, r5, r11, lr}
; CHECK-FP: push {r4, r5, r11, lr} ; CHECK-FP: push {r4, r5, r11, lr}
@ -239,7 +239,7 @@ entry:
; CHECK-FP: mov pc, lr ; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM: test3: ; CHECK-FP-ELIM-LABEL: test3:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r11, lr} ; CHECK-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r11, lr}
@ -247,7 +247,7 @@ entry:
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP: test3: ; CHECK-V7-FP-LABEL: test3:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r5, r11, lr} ; CHECK-V7-FP: .save {r4, r5, r11, lr}
; CHECK-V7-FP: push {r4, r5, r11, lr} ; CHECK-V7-FP: push {r4, r5, r11, lr}
@ -256,7 +256,7 @@ entry:
; CHECK-V7-FP: pop {r4, r5, r11, pc} ; CHECK-V7-FP: pop {r4, r5, r11, pc}
; CHECK-V7-FP: .fnend ; CHECK-V7-FP: .fnend
; CHECK-V7-FP-ELIM: test3: ; CHECK-V7-FP-ELIM-LABEL: test3:
; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr} ; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr} ; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr}
@ -273,25 +273,25 @@ entry:
ret void ret void
} }
; CHECK-FP: test4: ; CHECK-FP-LABEL: test4:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: mov pc, lr ; CHECK-FP: mov pc, lr
; CHECK-FP: .cantunwind ; CHECK-FP: .cantunwind
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM: test4: ; CHECK-FP-ELIM-LABEL: test4:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .cantunwind ; CHECK-FP-ELIM: .cantunwind
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP: test4: ; CHECK-V7-FP-LABEL: test4:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: bx lr ; CHECK-V7-FP: bx lr
; CHECK-V7-FP: .cantunwind ; CHECK-V7-FP: .cantunwind
; CHECK-V7-FP: .fnend ; CHECK-V7-FP: .fnend
; CHECK-V7-FP-ELIM: test4: ; CHECK-V7-FP-ELIM-LABEL: test4:
; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: bx lr ; CHECK-V7-FP-ELIM: bx lr
; CHECK-V7-FP-ELIM: .cantunwind ; CHECK-V7-FP-ELIM: .cantunwind

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@ -3,7 +3,7 @@
define void @foo(i16* %ptr, i32 %a) nounwind { define void @foo(i16* %ptr, i32 %a) nounwind {
entry: entry:
; CHECK: foo: ; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100 %tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2 br i1 %tmp1, label %bb1, label %bb2
bb1: bb1:

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@ -4,8 +4,8 @@
define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
entry: entry:
; THUMB: t1: ; THUMB-LABEL: t1:
; ARM: t1: ; ARM-LABEL: t1:
%x = add i32 %a, %b %x = add i32 %a, %b
br i1 1, label %if.then, label %if.else br i1 1, label %if.then, label %if.else
; THUMB-NOT: b {{\.?}}LBB0_1 ; THUMB-NOT: b {{\.?}}LBB0_1

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@ -17,54 +17,54 @@
; zext ; zext
define i8 @zext_1_8(i1 %a) nounwind ssp { define i8 @zext_1_8(i1 %a) nounwind ssp {
; v7: zext_1_8: ; v7-LABEL: zext_1_8:
; v7: and r0, r0, #1 ; v7: and r0, r0, #1
; prev6: zext_1_8: ; prev6-LABEL: zext_1_8:
; prev6: and r0, r0, #1 ; prev6: and r0, r0, #1
%r = zext i1 %a to i8 %r = zext i1 %a to i8
ret i8 %r ret i8 %r
} }
define i16 @zext_1_16(i1 %a) nounwind ssp { define i16 @zext_1_16(i1 %a) nounwind ssp {
; v7: zext_1_16: ; v7-LABEL: zext_1_16:
; v7: and r0, r0, #1 ; v7: and r0, r0, #1
; prev6: zext_1_16: ; prev6-LABEL: zext_1_16:
; prev6: and r0, r0, #1 ; prev6: and r0, r0, #1
%r = zext i1 %a to i16 %r = zext i1 %a to i16
ret i16 %r ret i16 %r
} }
define i32 @zext_1_32(i1 %a) nounwind ssp { define i32 @zext_1_32(i1 %a) nounwind ssp {
; v7: zext_1_32: ; v7-LABEL: zext_1_32:
; v7: and r0, r0, #1 ; v7: and r0, r0, #1
; prev6: zext_1_32: ; prev6-LABEL: zext_1_32:
; prev6: and r0, r0, #1 ; prev6: and r0, r0, #1
%r = zext i1 %a to i32 %r = zext i1 %a to i32
ret i32 %r ret i32 %r
} }
define i16 @zext_8_16(i8 %a) nounwind ssp { define i16 @zext_8_16(i8 %a) nounwind ssp {
; v7: zext_8_16: ; v7-LABEL: zext_8_16:
; v7: and r0, r0, #255 ; v7: and r0, r0, #255
; prev6: zext_8_16: ; prev6-LABEL: zext_8_16:
; prev6: and r0, r0, #255 ; prev6: and r0, r0, #255
%r = zext i8 %a to i16 %r = zext i8 %a to i16
ret i16 %r ret i16 %r
} }
define i32 @zext_8_32(i8 %a) nounwind ssp { define i32 @zext_8_32(i8 %a) nounwind ssp {
; v7: zext_8_32: ; v7-LABEL: zext_8_32:
; v7: and r0, r0, #255 ; v7: and r0, r0, #255
; prev6: zext_8_32: ; prev6-LABEL: zext_8_32:
; prev6: and r0, r0, #255 ; prev6: and r0, r0, #255
%r = zext i8 %a to i32 %r = zext i8 %a to i32
ret i32 %r ret i32 %r
} }
define i32 @zext_16_32(i16 %a) nounwind ssp { define i32 @zext_16_32(i16 %a) nounwind ssp {
; v7: zext_16_32: ; v7-LABEL: zext_16_32:
; v7: uxth r0, r0 ; v7: uxth r0, r0
; prev6: zext_16_32: ; prev6-LABEL: zext_16_32:
; prev6: lsl{{s?}} r0, r0, #16 ; prev6: lsl{{s?}} r0, r0, #16
; prev6: lsr{{s?}} r0, r0, #16 ; prev6: lsr{{s?}} r0, r0, #16
%r = zext i16 %a to i32 %r = zext i16 %a to i32
@ -74,10 +74,10 @@ define i32 @zext_16_32(i16 %a) nounwind ssp {
; sext ; sext
define i8 @sext_1_8(i1 %a) nounwind ssp { define i8 @sext_1_8(i1 %a) nounwind ssp {
; v7: sext_1_8: ; v7-LABEL: sext_1_8:
; v7: lsl{{s?}} r0, r0, #31 ; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31
; prev6: sext_1_8: ; prev6-LABEL: sext_1_8:
; prev6: lsl{{s?}} r0, r0, #31 ; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i8 %r = sext i1 %a to i8
@ -85,10 +85,10 @@ define i8 @sext_1_8(i1 %a) nounwind ssp {
} }
define i16 @sext_1_16(i1 %a) nounwind ssp { define i16 @sext_1_16(i1 %a) nounwind ssp {
; v7: sext_1_16: ; v7-LABEL: sext_1_16:
; v7: lsl{{s?}} r0, r0, #31 ; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31
; prev6: sext_1_16: ; prev6-LABEL: sext_1_16:
; prev6: lsl{{s?}} r0, r0, #31 ; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i16 %r = sext i1 %a to i16
@ -96,10 +96,10 @@ define i16 @sext_1_16(i1 %a) nounwind ssp {
} }
define i32 @sext_1_32(i1 %a) nounwind ssp { define i32 @sext_1_32(i1 %a) nounwind ssp {
; v7: sext_1_32: ; v7-LABEL: sext_1_32:
; v7: lsl{{s?}} r0, r0, #31 ; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31
; prev6: sext_1_32: ; prev6-LABEL: sext_1_32:
; prev6: lsl{{s?}} r0, r0, #31 ; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i32 %r = sext i1 %a to i32
@ -107,9 +107,9 @@ define i32 @sext_1_32(i1 %a) nounwind ssp {
} }
define i16 @sext_8_16(i8 %a) nounwind ssp { define i16 @sext_8_16(i8 %a) nounwind ssp {
; v7: sext_8_16: ; v7-LABEL: sext_8_16:
; v7: sxtb r0, r0 ; v7: sxtb r0, r0
; prev6: sext_8_16: ; prev6-LABEL: sext_8_16:
; prev6: lsl{{s?}} r0, r0, #24 ; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24 ; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i16 %r = sext i8 %a to i16
@ -117,9 +117,9 @@ define i16 @sext_8_16(i8 %a) nounwind ssp {
} }
define i32 @sext_8_32(i8 %a) nounwind ssp { define i32 @sext_8_32(i8 %a) nounwind ssp {
; v7: sext_8_32: ; v7-LABEL: sext_8_32:
; v7: sxtb r0, r0 ; v7: sxtb r0, r0
; prev6: sext_8_32: ; prev6-LABEL: sext_8_32:
; prev6: lsl{{s?}} r0, r0, #24 ; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24 ; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i32 %r = sext i8 %a to i32
@ -127,9 +127,9 @@ define i32 @sext_8_32(i8 %a) nounwind ssp {
} }
define i32 @sext_16_32(i16 %a) nounwind ssp { define i32 @sext_16_32(i16 %a) nounwind ssp {
; v7: sext_16_32: ; v7-LABEL: sext_16_32:
; v7: sxth r0, r0 ; v7: sxth r0, r0
; prev6: sext_16_32: ; prev6-LABEL: sext_16_32:
; prev6: lsl{{s?}} r0, r0, #16 ; prev6: lsl{{s?}} r0, r0, #16
; prev6: asr{{s?}} r0, r0, #16 ; prev6: asr{{s?}} r0, r0, #16
%r = sext i16 %a to i32 %r = sext i16 %a to i32

View File

@ -5,22 +5,22 @@
define i8* @frameaddr_index0() nounwind { define i8* @frameaddr_index0() nounwind {
entry: entry:
; DARWIN-ARM: frameaddr_index0: ; DARWIN-ARM-LABEL: frameaddr_index0:
; DARWIN-ARM: push {r7} ; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7 ; DARWIN-ARM: mov r0, r7
; DARWIN-THUMB2: frameaddr_index0: ; DARWIN-THUMB2-LABEL: frameaddr_index0:
; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7 ; DARWIN-THUMB2: mov r0, r7
; LINUX-ARM: frameaddr_index0: ; LINUX-ARM-LABEL: frameaddr_index0:
; LINUX-ARM: push {r11} ; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp ; LINUX-ARM: mov r11, sp
; LINUX-ARM: mov r0, r11 ; LINUX-ARM: mov r0, r11
; LINUX-THUMB2: frameaddr_index0: ; LINUX-THUMB2-LABEL: frameaddr_index0:
; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7 ; LINUX-THUMB2: mov r0, r7
@ -31,24 +31,24 @@ entry:
define i8* @frameaddr_index1() nounwind { define i8* @frameaddr_index1() nounwind {
entry: entry:
; DARWIN-ARM: frameaddr_index1: ; DARWIN-ARM-LABEL: frameaddr_index1:
; DARWIN-ARM: push {r7} ; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7 ; DARWIN-ARM: mov r0, r7
; DARWIN-ARM: ldr r0, [r0] ; DARWIN-ARM: ldr r0, [r0]
; DARWIN-THUMB2: frameaddr_index1: ; DARWIN-THUMB2-LABEL: frameaddr_index1:
; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7 ; DARWIN-THUMB2: mov r0, r7
; DARWIN-THUMB2: ldr r0, [r0] ; DARWIN-THUMB2: ldr r0, [r0]
; LINUX-ARM: frameaddr_index1: ; LINUX-ARM-LABEL: frameaddr_index1:
; LINUX-ARM: push {r11} ; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp ; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11] ; LINUX-ARM: ldr r0, [r11]
; LINUX-THUMB2: frameaddr_index1: ; LINUX-THUMB2-LABEL: frameaddr_index1:
; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7 ; LINUX-THUMB2: mov r0, r7
@ -60,7 +60,7 @@ entry:
define i8* @frameaddr_index3() nounwind { define i8* @frameaddr_index3() nounwind {
entry: entry:
; DARWIN-ARM: frameaddr_index3: ; DARWIN-ARM-LABEL: frameaddr_index3:
; DARWIN-ARM: push {r7} ; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7 ; DARWIN-ARM: mov r0, r7
@ -68,7 +68,7 @@ entry:
; DARWIN-ARM: ldr r0, [r0] ; DARWIN-ARM: ldr r0, [r0]
; DARWIN-ARM: ldr r0, [r0] ; DARWIN-ARM: ldr r0, [r0]
; DARWIN-THUMB2: frameaddr_index3: ; DARWIN-THUMB2-LABEL: frameaddr_index3:
; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7 ; DARWIN-THUMB2: mov r0, r7
@ -76,14 +76,14 @@ entry:
; DARWIN-THUMB2: ldr r0, [r0] ; DARWIN-THUMB2: ldr r0, [r0]
; DARWIN-THUMB2: ldr r0, [r0] ; DARWIN-THUMB2: ldr r0, [r0]
; LINUX-ARM: frameaddr_index3: ; LINUX-ARM-LABEL: frameaddr_index3:
; LINUX-ARM: push {r11} ; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp ; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11] ; LINUX-ARM: ldr r0, [r11]
; LINUX-ARM: ldr r0, [r0] ; LINUX-ARM: ldr r0, [r0]
; LINUX-ARM: ldr r0, [r0] ; LINUX-ARM: ldr r0, [r0]
; LINUX-THUMB2: frameaddr_index3: ; LINUX-THUMB2-LABEL: frameaddr_index3:
; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7 ; LINUX-THUMB2: mov r0, r7

View File

@ -6,13 +6,13 @@
define float @t1(float %acc, float %a, float %b) { define float @t1(float %acc, float %a, float %b) {
entry: entry:
; VFP2: t1: ; VFP2-LABEL: t1:
; VFP2: vmla.f32 ; VFP2: vmla.f32
; NEON: t1: ; NEON-LABEL: t1:
; NEON: vmla.f32 ; NEON: vmla.f32
; A8: t1: ; A8-LABEL: t1:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vadd.f32 ; A8: vadd.f32
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -22,13 +22,13 @@ entry:
define double @t2(double %acc, double %a, double %b) { define double @t2(double %acc, double %a, double %b) {
entry: entry:
; VFP2: t2: ; VFP2-LABEL: t2:
; VFP2: vmla.f64 ; VFP2: vmla.f64
; NEON: t2: ; NEON-LABEL: t2:
; NEON: vmla.f64 ; NEON: vmla.f64
; A8: t2: ; A8-LABEL: t2:
; A8: vmul.f64 ; A8: vmul.f64
; A8: vadd.f64 ; A8: vadd.f64
%0 = fmul double %a, %b %0 = fmul double %a, %b
@ -38,13 +38,13 @@ entry:
define float @t3(float %acc, float %a, float %b) { define float @t3(float %acc, float %a, float %b) {
entry: entry:
; VFP2: t3: ; VFP2-LABEL: t3:
; VFP2: vmla.f32 ; VFP2: vmla.f32
; NEON: t3: ; NEON-LABEL: t3:
; NEON: vmla.f32 ; NEON: vmla.f32
; A8: t3: ; A8-LABEL: t3:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vadd.f32 ; A8: vadd.f32
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -56,18 +56,18 @@ entry:
; rdar://8659675 ; rdar://8659675
define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) { define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
entry: entry:
; A8: t4: ; A8-LABEL: t4:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vmul.f32 ; A8: vmul.f32
; A8: vadd.f32 ; A8: vadd.f32
; A8: vadd.f32 ; A8: vadd.f32
; Two vmla with now RAW hazard ; Two vmla with now RAW hazard
; A9: t4: ; A9-LABEL: t4:
; A9: vmla.f32 ; A9: vmla.f32
; A9: vmla.f32 ; A9: vmla.f32
; HARD: t4: ; HARD-LABEL: t4:
; HARD: vmla.f32 s0, s1, s2 ; HARD: vmla.f32 s0, s1, s2
; HARD: vmla.f32 s3, s1, s4 ; HARD: vmla.f32 s3, s1, s4
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -81,18 +81,18 @@ entry:
define float @t5(float %a, float %b, float %c, float %d, float %e) { define float @t5(float %a, float %b, float %c, float %d, float %e) {
entry: entry:
; A8: t5: ; A8-LABEL: t5:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vmul.f32 ; A8: vmul.f32
; A8: vadd.f32 ; A8: vadd.f32
; A8: vadd.f32 ; A8: vadd.f32
; A9: t5: ; A9-LABEL: t5:
; A9: vmla.f32 ; A9: vmla.f32
; A9: vmul.f32 ; A9: vmul.f32
; A9: vadd.f32 ; A9: vadd.f32
; HARD: t5: ; HARD-LABEL: t5:
; HARD: vmla.f32 s4, s0, s1 ; HARD: vmla.f32 s4, s0, s1
; HARD: vmul.f32 s0, s2, s3 ; HARD: vmul.f32 s0, s2, s3
; HARD: vadd.f32 s0, s4, s0 ; HARD: vadd.f32 s0, s4, s0

View File

@ -4,13 +4,13 @@
define float @t1(float %acc, float %a, float %b) { define float @t1(float %acc, float %a, float %b) {
entry: entry:
; VFP2: t1: ; VFP2-LABEL: t1:
; VFP2: vnmls.f32 ; VFP2: vnmls.f32
; NEON: t1: ; NEON-LABEL: t1:
; NEON: vnmls.f32 ; NEON: vnmls.f32
; A8: t1: ; A8-LABEL: t1:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vsub.f32 ; A8: vsub.f32
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -20,13 +20,13 @@ entry:
define double @t2(double %acc, double %a, double %b) { define double @t2(double %acc, double %a, double %b) {
entry: entry:
; VFP2: t2: ; VFP2-LABEL: t2:
; VFP2: vnmls.f64 ; VFP2: vnmls.f64
; NEON: t2: ; NEON-LABEL: t2:
; NEON: vnmls.f64 ; NEON: vnmls.f64
; A8: t2: ; A8-LABEL: t2:
; A8: vmul.f64 ; A8: vmul.f64
; A8: vsub.f64 ; A8: vsub.f64
%0 = fmul double %a, %b %0 = fmul double %a, %b

View File

@ -4,13 +4,13 @@
define float @t1(float %acc, float %a, float %b) { define float @t1(float %acc, float %a, float %b) {
entry: entry:
; VFP2: t1: ; VFP2-LABEL: t1:
; VFP2: vmls.f32 ; VFP2: vmls.f32
; NEON: t1: ; NEON-LABEL: t1:
; NEON: vmls.f32 ; NEON: vmls.f32
; A8: t1: ; A8-LABEL: t1:
; A8: vmul.f32 ; A8: vmul.f32
; A8: vsub.f32 ; A8: vsub.f32
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -20,13 +20,13 @@ entry:
define double @t2(double %acc, double %a, double %b) { define double @t2(double %acc, double %a, double %b) {
entry: entry:
; VFP2: t2: ; VFP2-LABEL: t2:
; VFP2: vmls.f64 ; VFP2: vmls.f64
; NEON: t2: ; NEON-LABEL: t2:
; NEON: vmls.f64 ; NEON: vmls.f64
; A8: t2: ; A8-LABEL: t2:
; A8: vmul.f64 ; A8: vmul.f64
; A8: vsub.f64 ; A8: vsub.f64
%0 = fmul double %a, %b %0 = fmul double %a, %b

View File

@ -7,17 +7,17 @@
define float @t1(float %acc, float %a, float %b) nounwind { define float @t1(float %acc, float %a, float %b) nounwind {
entry: entry:
; VFP2: t1: ; VFP2-LABEL: t1:
; VFP2: vnmla.f32 ; VFP2: vnmla.f32
; NEON: t1: ; NEON-LABEL: t1:
; NEON: vnmla.f32 ; NEON: vnmla.f32
; A8U: t1: ; A8U-LABEL: t1:
; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
; A8: t1: ; A8-LABEL: t1:
; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -28,17 +28,17 @@ entry:
define float @t2(float %acc, float %a, float %b) nounwind { define float @t2(float %acc, float %a, float %b) nounwind {
entry: entry:
; VFP2: t2: ; VFP2-LABEL: t2:
; VFP2: vnmla.f32 ; VFP2: vnmla.f32
; NEON: t2: ; NEON-LABEL: t2:
; NEON: vnmla.f32 ; NEON: vnmla.f32
; A8U: t2: ; A8U-LABEL: t2:
; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
; A8: t2: ; A8-LABEL: t2:
; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b %0 = fmul float %a, %b
@ -49,17 +49,17 @@ entry:
define double @t3(double %acc, double %a, double %b) nounwind { define double @t3(double %acc, double %a, double %b) nounwind {
entry: entry:
; VFP2: t3: ; VFP2-LABEL: t3:
; VFP2: vnmla.f64 ; VFP2: vnmla.f64
; NEON: t3: ; NEON-LABEL: t3:
; NEON: vnmla.f64 ; NEON: vnmla.f64
; A8U: t3: ; A8U-LABEL: t3:
; A8U: vnmul.f64 d ; A8U: vnmul.f64 d
; A8U: vsub.f64 d ; A8U: vsub.f64 d
; A8: t3: ; A8-LABEL: t3:
; A8: vnmul.f64 d ; A8: vnmul.f64 d
; A8: vsub.f64 d ; A8: vsub.f64 d
%0 = fmul double %a, %b %0 = fmul double %a, %b
@ -70,17 +70,17 @@ entry:
define double @t4(double %acc, double %a, double %b) nounwind { define double @t4(double %acc, double %a, double %b) nounwind {
entry: entry:
; VFP2: t4: ; VFP2-LABEL: t4:
; VFP2: vnmla.f64 ; VFP2: vnmla.f64
; NEON: t4: ; NEON-LABEL: t4:
; NEON: vnmla.f64 ; NEON: vnmla.f64
; A8U: t4: ; A8U-LABEL: t4:
; A8U: vnmul.f64 d ; A8U: vnmul.f64 d
; A8U: vsub.f64 d ; A8U: vsub.f64 d
; A8: t4: ; A8-LABEL: t4:
; A8: vnmul.f64 d ; A8: vnmul.f64 d
; A8: vsub.f64 d ; A8: vsub.f64 d
%0 = fmul double %a, %b %0 = fmul double %a, %b

View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f(i32 %a) { define float @f(i32 %a) {
;CHECK: f: ;CHECK-LABEL: f:
;CHECK: vmov ;CHECK: vmov
;CHECK-NEXT: vcvt.f32.s32 ;CHECK-NEXT: vcvt.f32.s32
;CHECK-NEXT: vmov ;CHECK-NEXT: vmov
@ -11,7 +11,7 @@ entry:
} }
define double @g(i32 %a) { define double @g(i32 %a) {
;CHECK: g: ;CHECK-LABEL: g:
;CHECK: vmov ;CHECK: vmov
;CHECK-NEXT: vcvt.f64.s32 ;CHECK-NEXT: vcvt.f64.s32
;CHECK-NEXT: vmov ;CHECK-NEXT: vmov
@ -21,7 +21,7 @@ entry:
} }
define double @uint_to_double(i32 %a) { define double @uint_to_double(i32 %a) {
;CHECK: uint_to_double: ;CHECK-LABEL: uint_to_double:
;CHECK: vmov ;CHECK: vmov
;CHECK-NEXT: vcvt.f64.u32 ;CHECK-NEXT: vcvt.f64.u32
;CHECK-NEXT: vmov ;CHECK-NEXT: vmov
@ -31,7 +31,7 @@ entry:
} }
define float @uint_to_float(i32 %a) { define float @uint_to_float(i32 %a) {
;CHECK: uint_to_float: ;CHECK-LABEL: uint_to_float:
;CHECK: vmov ;CHECK: vmov
;CHECK-NEXT: vcvt.f32.u32 ;CHECK-NEXT: vcvt.f32.u32
;CHECK-NEXT: vmov ;CHECK-NEXT: vmov
@ -41,7 +41,7 @@ entry:
} }
define double @h(double* %v) { define double @h(double* %v) {
;CHECK: h: ;CHECK-LABEL: h:
;CHECK: vldr ;CHECK: vldr
;CHECK-NEXT: vmov ;CHECK-NEXT: vmov
entry: entry:
@ -50,20 +50,20 @@ entry:
} }
define float @h2() { define float @h2() {
;CHECK: h2: ;CHECK-LABEL: h2:
;CHECK: mov r0, #1065353216 ;CHECK: mov r0, #1065353216
entry: entry:
ret float 1.000000e+00 ret float 1.000000e+00
} }
define double @f2(double %a) { define double @f2(double %a) {
;CHECK: f2: ;CHECK-LABEL: f2:
;CHECK-NOT: vmov ;CHECK-NOT: vmov
ret double %a ret double %a
} }
define void @f3() { define void @f3() {
;CHECK: f3: ;CHECK-LABEL: f3:
;CHECK-NOT: vmov ;CHECK-NOT: vmov
;CHECK: f4 ;CHECK: f4
entry: entry:

View File

@ -8,8 +8,8 @@ target triple = "armv7-eabi"
@z = common global i16 0 @z = common global i16 0
define arm_aapcs_vfpcc void @foo() nounwind { define arm_aapcs_vfpcc void @foo() nounwind {
; CHECK: foo: ; CHECK-LABEL: foo:
; CHECK-FP6: foo: ; CHECK-FP6-LABEL: foo:
entry: entry:
%0 = load i16* @x, align 2 %0 = load i16* @x, align 2
%1 = load i16* @y, align 2 %1 = load i16* @y, align 2

View File

@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
define float @f1(float %a, float %b) { define float @f1(float %a, float %b) {
;CHECK: f1: ;CHECK-LABEL: f1:
;CHECK: vadd.f32 ;CHECK: vadd.f32
entry: entry:
%tmp = fadd float %a, %b ; <float> [#uses=1] %tmp = fadd float %a, %b ; <float> [#uses=1]
@ -9,7 +9,7 @@ entry:
} }
define double @f2(double %a, double %b) { define double @f2(double %a, double %b) {
;CHECK: f2: ;CHECK-LABEL: f2:
;CHECK: vadd.f64 ;CHECK: vadd.f64
entry: entry:
%tmp = fadd double %a, %b ; <double> [#uses=1] %tmp = fadd double %a, %b ; <double> [#uses=1]
@ -17,7 +17,7 @@ entry:
} }
define float @f3(float %a, float %b) { define float @f3(float %a, float %b) {
;CHECK: f3: ;CHECK-LABEL: f3:
;CHECK: vmul.f32 ;CHECK: vmul.f32
entry: entry:
%tmp = fmul float %a, %b ; <float> [#uses=1] %tmp = fmul float %a, %b ; <float> [#uses=1]
@ -25,7 +25,7 @@ entry:
} }
define double @f4(double %a, double %b) { define double @f4(double %a, double %b) {
;CHECK: f4: ;CHECK-LABEL: f4:
;CHECK: vmul.f64 ;CHECK: vmul.f64
entry: entry:
%tmp = fmul double %a, %b ; <double> [#uses=1] %tmp = fmul double %a, %b ; <double> [#uses=1]
@ -33,7 +33,7 @@ entry:
} }
define float @f5(float %a, float %b) { define float @f5(float %a, float %b) {
;CHECK: f5: ;CHECK-LABEL: f5:
;CHECK: vsub.f32 ;CHECK: vsub.f32
entry: entry:
%tmp = fsub float %a, %b ; <float> [#uses=1] %tmp = fsub float %a, %b ; <float> [#uses=1]
@ -41,7 +41,7 @@ entry:
} }
define double @f6(double %a, double %b) { define double @f6(double %a, double %b) {
;CHECK: f6: ;CHECK-LABEL: f6:
;CHECK: vsub.f64 ;CHECK: vsub.f64
entry: entry:
%tmp = fsub double %a, %b ; <double> [#uses=1] %tmp = fsub double %a, %b ; <double> [#uses=1]
@ -49,7 +49,7 @@ entry:
} }
define float @f7(float %a) { define float @f7(float %a) {
;CHECK: f7: ;CHECK-LABEL: f7:
;CHECK: eor ;CHECK: eor
entry: entry:
%tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1] %tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
@ -57,7 +57,7 @@ entry:
} }
define double @f8(double %a) { define double @f8(double %a) {
;CHECK: f8: ;CHECK-LABEL: f8:
;CHECK: vneg.f64 ;CHECK: vneg.f64
entry: entry:
%tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1] %tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1]
@ -65,7 +65,7 @@ entry:
} }
define float @f9(float %a, float %b) { define float @f9(float %a, float %b) {
;CHECK: f9: ;CHECK-LABEL: f9:
;CHECK: vdiv.f32 ;CHECK: vdiv.f32
entry: entry:
%tmp1 = fdiv float %a, %b ; <float> [#uses=1] %tmp1 = fdiv float %a, %b ; <float> [#uses=1]
@ -73,7 +73,7 @@ entry:
} }
define double @f10(double %a, double %b) { define double @f10(double %a, double %b) {
;CHECK: f10: ;CHECK-LABEL: f10:
;CHECK: vdiv.f64 ;CHECK: vdiv.f64
entry: entry:
%tmp1 = fdiv double %a, %b ; <double> [#uses=1] %tmp1 = fdiv double %a, %b ; <double> [#uses=1]
@ -81,7 +81,7 @@ entry:
} }
define float @f11(float %a) { define float @f11(float %a) {
;CHECK: f11: ;CHECK-LABEL: f11:
;CHECK: bic ;CHECK: bic
entry: entry:
%tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1] %tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
@ -91,7 +91,7 @@ entry:
declare float @fabsf(float) declare float @fabsf(float)
define double @f12(double %a) { define double @f12(double %a) {
;CHECK: f12: ;CHECK-LABEL: f12:
;CHECK: vabs.f64 ;CHECK: vabs.f64
entry: entry:
%tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1] %tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1]

View File

@ -5,7 +5,7 @@
; Disable this optimization unless we know one of them is zero. ; Disable this optimization unless we know one of them is zero.
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
entry: entry:
; CHECK: t1: ; CHECK-LABEL: t1:
; CHECK: vldr [[S0:s[0-9]+]], ; CHECK: vldr [[S0:s[0-9]+]],
; CHECK: vldr [[S1:s[0-9]+]], ; CHECK: vldr [[S1:s[0-9]+]],
; CHECK: vcmpe.f32 [[S1]], [[S0]] ; CHECK: vcmpe.f32 [[S1]], [[S0]]
@ -29,7 +29,7 @@ bb2:
; +0.0 == -0.0 ; +0.0 == -0.0
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
entry: entry:
; CHECK: t2: ; CHECK-LABEL: t2:
; CHECK-NOT: vldr ; CHECK-NOT: vldr
; CHECK: ldr [[REG1:(r[0-9]+)]], [r0] ; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4] ; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
@ -55,7 +55,7 @@ bb2:
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind { define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
entry: entry:
; CHECK: t3: ; CHECK-LABEL: t3:
; CHECK-NOT: vldr ; CHECK-NOT: vldr
; CHECK: ldr [[REG3:(r[0-9]+)]], [r0] ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648

View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define i32 @f1(float %a) { define i32 @f1(float %a) {
;CHECK: f1: ;CHECK-LABEL: f1:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: movmi ;CHECK: movmi
entry: entry:
@ -11,7 +11,7 @@ entry:
} }
define i32 @f2(float %a) { define i32 @f2(float %a) {
;CHECK: f2: ;CHECK-LABEL: f2:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: moveq ;CHECK: moveq
entry: entry:
@ -21,7 +21,7 @@ entry:
} }
define i32 @f3(float %a) { define i32 @f3(float %a) {
;CHECK: f3: ;CHECK-LABEL: f3:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: movgt ;CHECK: movgt
entry: entry:
@ -31,7 +31,7 @@ entry:
} }
define i32 @f4(float %a) { define i32 @f4(float %a) {
;CHECK: f4: ;CHECK-LABEL: f4:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: movge ;CHECK: movge
entry: entry:
@ -41,7 +41,7 @@ entry:
} }
define i32 @f5(float %a) { define i32 @f5(float %a) {
;CHECK: f5: ;CHECK-LABEL: f5:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: movls ;CHECK: movls
entry: entry:
@ -51,7 +51,7 @@ entry:
} }
define i32 @f6(float %a) { define i32 @f6(float %a) {
;CHECK: f6: ;CHECK-LABEL: f6:
;CHECK: vcmpe.f32 ;CHECK: vcmpe.f32
;CHECK: movne ;CHECK: movne
entry: entry:
@ -61,7 +61,7 @@ entry:
} }
define i32 @g1(double %a) { define i32 @g1(double %a) {
;CHECK: g1: ;CHECK-LABEL: g1:
;CHECK: vcmpe.f64 ;CHECK: vcmpe.f64
;CHECK: movmi ;CHECK: movmi
entry: entry:

View File

@ -3,7 +3,7 @@
define i32 @f7(float %a, float %b) { define i32 @f7(float %a, float %b) {
entry: entry:
; CHECK: f7: ; CHECK-LABEL: f7:
; CHECK: vcmpe.f32 ; CHECK: vcmpe.f32
; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: movweq ; CHECK: movweq

View File

@ -2,7 +2,7 @@
define float @t1(float %x) nounwind readnone optsize { define float @t1(float %x) nounwind readnone optsize {
entry: entry:
; CHECK: t1: ; CHECK-LABEL: t1:
; CHECK: vmov.f32 s{{.*}}, #4.000000e+00 ; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
%0 = fadd float %x, 4.000000e+00 %0 = fadd float %x, 4.000000e+00
ret float %0 ret float %0
@ -10,7 +10,7 @@ entry:
define double @t2(double %x) nounwind readnone optsize { define double @t2(double %x) nounwind readnone optsize {
entry: entry:
; CHECK: t2: ; CHECK-LABEL: t2:
; CHECK: vmov.f64 d{{.*}}, #3.000000e+00 ; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
%0 = fadd double %x, 3.000000e+00 %0 = fadd double %x, 3.000000e+00
ret double %0 ret double %0
@ -18,7 +18,7 @@ entry:
define double @t3(double %x) nounwind readnone optsize { define double @t3(double %x) nounwind readnone optsize {
entry: entry:
; CHECK: t3: ; CHECK-LABEL: t3:
; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01 ; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
%0 = fmul double %x, -1.300000e+01 %0 = fmul double %x, -1.300000e+01
ret double %0 ret double %0
@ -26,7 +26,7 @@ entry:
define float @t4(float %x) nounwind readnone optsize { define float @t4(float %x) nounwind readnone optsize {
entry: entry:
; CHECK: t4: ; CHECK-LABEL: t4:
; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01 ; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
%0 = fmul float %x, -2.400000e+01 %0 = fmul float %x, -2.400000e+01
ret float %0 ret float %0

View File

@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
define float @f1(double %x) { define float @f1(double %x) {
;CHECK-VFP: f1: ;CHECK-VFP-LABEL: f1:
;CHECK-VFP: vcvt.f32.f64 ;CHECK-VFP: vcvt.f32.f64
;CHECK: f1: ;CHECK-LABEL: f1:
;CHECK: truncdfsf2 ;CHECK: truncdfsf2
entry: entry:
%tmp1 = fptrunc double %x to float ; <float> [#uses=1] %tmp1 = fptrunc double %x to float ; <float> [#uses=1]
@ -12,9 +12,9 @@ entry:
} }
define double @f2(float %x) { define double @f2(float %x) {
;CHECK-VFP: f2: ;CHECK-VFP-LABEL: f2:
;CHECK-VFP: vcvt.f64.f32 ;CHECK-VFP: vcvt.f64.f32
;CHECK: f2: ;CHECK-LABEL: f2:
;CHECK: extendsfdf2 ;CHECK: extendsfdf2
entry: entry:
%tmp1 = fpext float %x to double ; <double> [#uses=1] %tmp1 = fpext float %x to double ; <double> [#uses=1]
@ -22,9 +22,9 @@ entry:
} }
define i32 @f3(float %x) { define i32 @f3(float %x) {
;CHECK-VFP: f3: ;CHECK-VFP-LABEL: f3:
;CHECK-VFP: vcvt.s32.f32 ;CHECK-VFP: vcvt.s32.f32
;CHECK: f3: ;CHECK-LABEL: f3:
;CHECK: fixsfsi ;CHECK: fixsfsi
entry: entry:
%tmp = fptosi float %x to i32 ; <i32> [#uses=1] %tmp = fptosi float %x to i32 ; <i32> [#uses=1]
@ -32,9 +32,9 @@ entry:
} }
define i32 @f4(float %x) { define i32 @f4(float %x) {
;CHECK-VFP: f4: ;CHECK-VFP-LABEL: f4:
;CHECK-VFP: vcvt.u32.f32 ;CHECK-VFP: vcvt.u32.f32
;CHECK: f4: ;CHECK-LABEL: f4:
;CHECK: fixunssfsi ;CHECK: fixunssfsi
entry: entry:
%tmp = fptoui float %x to i32 ; <i32> [#uses=1] %tmp = fptoui float %x to i32 ; <i32> [#uses=1]
@ -42,9 +42,9 @@ entry:
} }
define i32 @f5(double %x) { define i32 @f5(double %x) {
;CHECK-VFP: f5: ;CHECK-VFP-LABEL: f5:
;CHECK-VFP: vcvt.s32.f64 ;CHECK-VFP: vcvt.s32.f64
;CHECK: f5: ;CHECK-LABEL: f5:
;CHECK: fixdfsi ;CHECK: fixdfsi
entry: entry:
%tmp = fptosi double %x to i32 ; <i32> [#uses=1] %tmp = fptosi double %x to i32 ; <i32> [#uses=1]
@ -52,9 +52,9 @@ entry:
} }
define i32 @f6(double %x) { define i32 @f6(double %x) {
;CHECK-VFP: f6: ;CHECK-VFP-LABEL: f6:
;CHECK-VFP: vcvt.u32.f64 ;CHECK-VFP: vcvt.u32.f64
;CHECK: f6: ;CHECK-LABEL: f6:
;CHECK: fixunsdfsi ;CHECK: fixunsdfsi
entry: entry:
%tmp = fptoui double %x to i32 ; <i32> [#uses=1] %tmp = fptoui double %x to i32 ; <i32> [#uses=1]
@ -62,9 +62,9 @@ entry:
} }
define float @f7(i32 %a) { define float @f7(i32 %a) {
;CHECK-VFP: f7: ;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vcvt.f32.s32 ;CHECK-VFP: vcvt.f32.s32
;CHECK: f7: ;CHECK-LABEL: f7:
;CHECK: floatsisf ;CHECK: floatsisf
entry: entry:
%tmp = sitofp i32 %a to float ; <float> [#uses=1] %tmp = sitofp i32 %a to float ; <float> [#uses=1]
@ -72,9 +72,9 @@ entry:
} }
define double @f8(i32 %a) { define double @f8(i32 %a) {
;CHECK-VFP: f8: ;CHECK-VFP-LABEL: f8:
;CHECK-VFP: vcvt.f64.s32 ;CHECK-VFP: vcvt.f64.s32
;CHECK: f8: ;CHECK-LABEL: f8:
;CHECK: floatsidf ;CHECK: floatsidf
entry: entry:
%tmp = sitofp i32 %a to double ; <double> [#uses=1] %tmp = sitofp i32 %a to double ; <double> [#uses=1]
@ -82,9 +82,9 @@ entry:
} }
define float @f9(i32 %a) { define float @f9(i32 %a) {
;CHECK-VFP: f9: ;CHECK-VFP-LABEL: f9:
;CHECK-VFP: vcvt.f32.u32 ;CHECK-VFP: vcvt.f32.u32
;CHECK: f9: ;CHECK-LABEL: f9:
;CHECK: floatunsisf ;CHECK: floatunsisf
entry: entry:
%tmp = uitofp i32 %a to float ; <float> [#uses=1] %tmp = uitofp i32 %a to float ; <float> [#uses=1]
@ -92,9 +92,9 @@ entry:
} }
define double @f10(i32 %a) { define double @f10(i32 %a) {
;CHECK-VFP: f10: ;CHECK-VFP-LABEL: f10:
;CHECK-VFP: vcvt.f64.u32 ;CHECK-VFP: vcvt.f64.u32
;CHECK: f10: ;CHECK-LABEL: f10:
;CHECK: floatunsidf ;CHECK: floatunsidf
entry: entry:
%tmp = uitofp i32 %a to double ; <double> [#uses=1] %tmp = uitofp i32 %a to double ; <double> [#uses=1]

View File

@ -1,13 +1,13 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) { define float @f1(float %a) {
; CHECK: f1: ; CHECK-LABEL: f1:
; CHECK: mov r0, #0 ; CHECK: mov r0, #0
ret float 0.000000e+00 ret float 0.000000e+00
} }
define float @f2(float* %v, float %u) { define float @f2(float* %v, float %u) {
; CHECK: f2: ; CHECK-LABEL: f2:
; CHECK: vldr{{.*}}[ ; CHECK: vldr{{.*}}[
%tmp = load float* %v ; <float> [#uses=1] %tmp = load float* %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1] %tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
@ -15,7 +15,7 @@ define float @f2(float* %v, float %u) {
} }
define float @f2offset(float* %v, float %u) { define float @f2offset(float* %v, float %u) {
; CHECK: f2offset: ; CHECK-LABEL: f2offset:
; CHECK: vldr{{.*}}, #4] ; CHECK: vldr{{.*}}, #4]
%addr = getelementptr float* %v, i32 1 %addr = getelementptr float* %v, i32 1
%tmp = load float* %addr %tmp = load float* %addr
@ -24,7 +24,7 @@ define float @f2offset(float* %v, float %u) {
} }
define float @f2noffset(float* %v, float %u) { define float @f2noffset(float* %v, float %u) {
; CHECK: f2noffset: ; CHECK-LABEL: f2noffset:
; CHECK: vldr{{.*}}, #-4] ; CHECK: vldr{{.*}}, #-4]
%addr = getelementptr float* %v, i32 -1 %addr = getelementptr float* %v, i32 -1
%tmp = load float* %addr %tmp = load float* %addr
@ -33,7 +33,7 @@ define float @f2noffset(float* %v, float %u) {
} }
define void @f3(float %a, float %b, float* %v) { define void @f3(float %a, float %b, float* %v) {
; CHECK: f3: ; CHECK-LABEL: f3:
; CHECK: vstr{{.*}}[ ; CHECK: vstr{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1] %tmp = fadd float %a, %b ; <float> [#uses=1]
store float %tmp, float* %v store float %tmp, float* %v

View File

@ -44,6 +44,6 @@ define void @foo9(double %x) {
store i16 %tmp, i16* null store i16 %tmp, i16* null
ret void ret void
} }
; CHECK: foo9: ; CHECK-LABEL: foo9:
; CHECK: vmov r0, s0 ; CHECK: vmov r0, s0

View File

@ -2,7 +2,7 @@
; Check generated fused MAC and MLS. ; Check generated fused MAC and MLS.
define double @fusedMACTest1(double %d1, double %d2, double %d3) { define double @fusedMACTest1(double %d1, double %d2, double %d3) {
;CHECK: fusedMACTest1: ;CHECK-LABEL: fusedMACTest1:
;CHECK: vfma.f64 ;CHECK: vfma.f64
%1 = fmul double %d1, %d2 %1 = fmul double %d1, %d2
%2 = fadd double %1, %d3 %2 = fadd double %1, %d3
@ -10,7 +10,7 @@ define double @fusedMACTest1(double %d1, double %d2, double %d3) {
} }
define float @fusedMACTest2(float %f1, float %f2, float %f3) { define float @fusedMACTest2(float %f1, float %f2, float %f3) {
;CHECK: fusedMACTest2: ;CHECK-LABEL: fusedMACTest2:
;CHECK: vfma.f32 ;CHECK: vfma.f32
%1 = fmul float %f1, %f2 %1 = fmul float %f1, %f2
%2 = fadd float %1, %f3 %2 = fadd float %1, %f3
@ -18,7 +18,7 @@ define float @fusedMACTest2(float %f1, float %f2, float %f3) {
} }
define double @fusedMACTest3(double %d1, double %d2, double %d3) { define double @fusedMACTest3(double %d1, double %d2, double %d3) {
;CHECK: fusedMACTest3: ;CHECK-LABEL: fusedMACTest3:
;CHECK: vfms.f64 ;CHECK: vfms.f64
%1 = fmul double %d2, %d3 %1 = fmul double %d2, %d3
%2 = fsub double %d1, %1 %2 = fsub double %d1, %1
@ -26,7 +26,7 @@ define double @fusedMACTest3(double %d1, double %d2, double %d3) {
} }
define float @fusedMACTest4(float %f1, float %f2, float %f3) { define float @fusedMACTest4(float %f1, float %f2, float %f3) {
;CHECK: fusedMACTest4: ;CHECK-LABEL: fusedMACTest4:
;CHECK: vfms.f32 ;CHECK: vfms.f32
%1 = fmul float %f2, %f3 %1 = fmul float %f2, %f3
%2 = fsub float %f1, %1 %2 = fsub float %f1, %1
@ -34,7 +34,7 @@ define float @fusedMACTest4(float %f1, float %f2, float %f3) {
} }
define double @fusedMACTest5(double %d1, double %d2, double %d3) { define double @fusedMACTest5(double %d1, double %d2, double %d3) {
;CHECK: fusedMACTest5: ;CHECK-LABEL: fusedMACTest5:
;CHECK: vfnma.f64 ;CHECK: vfnma.f64
%1 = fmul double %d1, %d2 %1 = fmul double %d1, %d2
%2 = fsub double -0.0, %1 %2 = fsub double -0.0, %1
@ -43,7 +43,7 @@ define double @fusedMACTest5(double %d1, double %d2, double %d3) {
} }
define float @fusedMACTest6(float %f1, float %f2, float %f3) { define float @fusedMACTest6(float %f1, float %f2, float %f3) {
;CHECK: fusedMACTest6: ;CHECK-LABEL: fusedMACTest6:
;CHECK: vfnma.f32 ;CHECK: vfnma.f32
%1 = fmul float %f1, %f2 %1 = fmul float %f1, %f2
%2 = fsub float -0.0, %1 %2 = fsub float -0.0, %1
@ -52,7 +52,7 @@ define float @fusedMACTest6(float %f1, float %f2, float %f3) {
} }
define double @fusedMACTest7(double %d1, double %d2, double %d3) { define double @fusedMACTest7(double %d1, double %d2, double %d3) {
;CHECK: fusedMACTest7: ;CHECK-LABEL: fusedMACTest7:
;CHECK: vfnms.f64 ;CHECK: vfnms.f64
%1 = fmul double %d1, %d2 %1 = fmul double %d1, %d2
%2 = fsub double %1, %d3 %2 = fsub double %1, %d3
@ -60,7 +60,7 @@ define double @fusedMACTest7(double %d1, double %d2, double %d3) {
} }
define float @fusedMACTest8(float %f1, float %f2, float %f3) { define float @fusedMACTest8(float %f1, float %f2, float %f3) {
;CHECK: fusedMACTest8: ;CHECK-LABEL: fusedMACTest8:
;CHECK: vfnms.f32 ;CHECK: vfnms.f32
%1 = fmul float %f1, %f2 %1 = fmul float %f1, %f2
%2 = fsub float %1, %f3 %2 = fsub float %1, %f3
@ -68,7 +68,7 @@ define float @fusedMACTest8(float %f1, float %f2, float %f3) {
} }
define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) { define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
;CHECK: fusedMACTest9: ;CHECK-LABEL: fusedMACTest9:
;CHECK: vfma.f32 ;CHECK: vfma.f32
%mul = fmul <2 x float> %a, %b %mul = fmul <2 x float> %a, %b
%add = fadd <2 x float> %mul, %a %add = fadd <2 x float> %mul, %a
@ -76,7 +76,7 @@ define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
} }
define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) { define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
;CHECK: fusedMACTest10: ;CHECK-LABEL: fusedMACTest10:
;CHECK: vfms.f32 ;CHECK: vfms.f32
%mul = fmul <2 x float> %a, %b %mul = fmul <2 x float> %a, %b
%sub = fsub <2 x float> %a, %mul %sub = fsub <2 x float> %a, %mul
@ -84,7 +84,7 @@ define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
} }
define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) { define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
;CHECK: fusedMACTest11: ;CHECK-LABEL: fusedMACTest11:
;CHECK: vfma.f32 ;CHECK: vfma.f32
%mul = fmul <4 x float> %a, %b %mul = fmul <4 x float> %a, %b
%add = fadd <4 x float> %mul, %a %add = fadd <4 x float> %mul, %a
@ -92,7 +92,7 @@ define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
} }
define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) { define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) {
;CHECK: fusedMACTest12: ;CHECK-LABEL: fusedMACTest12:
;CHECK: vfms.f32 ;CHECK: vfms.f32
%mul = fmul <4 x float> %a, %b %mul = fmul <4 x float> %a, %b
%sub = fsub <4 x float> %a, %mul %sub = fsub <4 x float> %a, %mul

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@ -57,7 +57,7 @@ define i32 @test1() {
; LinuxPIC: test1: ; LinuxPIC-LABEL: test1:
; LinuxPIC: ldr r0, .LCPI0_0 ; LinuxPIC: ldr r0, .LCPI0_0
; LinuxPIC: ldr r1, .LCPI0_1 ; LinuxPIC: ldr r1, .LCPI0_1

View File

@ -4,7 +4,7 @@
define i32 @t() nounwind readonly { define i32 @t() nounwind readonly {
entry: entry:
; CHECK: t: ; CHECK-LABEL: t:
; CHECK: ldr ; CHECK: ldr
; CHECK-NEXT: ldr ; CHECK-NEXT: ldr
%0 = load i32* @x, align 4 ; <i32> [#uses=1] %0 = load i32* @x, align 4 ; <i32> [#uses=1]

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@ -6,18 +6,18 @@
define weak hidden void @t1() nounwind { define weak hidden void @t1() nounwind {
; LINUX: .hidden t1 ; LINUX: .hidden t1
; LINUX: t1: ; LINUX-LABEL: t1:
; DARWIN: .private_extern _t1 ; DARWIN: .private_extern _t1
; DARWIN: t1: ; DARWIN-LABEL: t1:
ret void ret void
} }
define weak void @t2() nounwind { define weak void @t2() nounwind {
; LINUX: t2: ; LINUX-LABEL: t2:
; LINUX: .hidden a ; LINUX: .hidden a
; DARWIN: t2: ; DARWIN-LABEL: t2:
; DARWIN: .private_extern _a ; DARWIN: .private_extern _a
ret void ret void
} }

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