RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-18 10:32:48 +02:00
Code Issues Projects Releases Wiki Activity

Use subregs to improve any_extend code generation when feasible.

Browse Source 
llvm-svn: 41013
This commit is contained in:
Christopher Lamb 2007-08-10 22:22:41 +00:00
parent 6c79abee5d
commit 7e52a97df5
3 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
CREDITS.TXT
View File

@ -135,7 +135,8 @@ D: Author of the original C backend
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support
D: aligned load/store support, parts of noalias and restrict support
D: vreg subreg infrastructure, X86 codegen improvements based on subregs
N: Jim Laskey
E: jlaskey@apple.com

16
lib/Target/X86/README.txt
View File

@ -532,22 +532,6 @@ the load's chain result is read by the callseq_start.
//===---------------------------------------------------------------------===//
Don't forget to find a way to squash noop truncates in the JIT environment.
//===---------------------------------------------------------------------===//
Implement anyext in the same manner as truncate that would allow them to be
eliminated.
//===---------------------------------------------------------------------===//
How about implementing truncate / anyext as a property of machine instruction
operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
//===---------------------------------------------------------------------===//
For this:
int test(int a)

33
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1372,6 +1372,39 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
return NULL;
}
case ISD::ANY_EXTEND: {
SDOperand N0 = Node->getOperand(0);
AddToISelQueue(N0);
if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
SDOperand SRIdx;
switch(N0.getValueType()) {
case MVT::i32:
SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
break;
case MVT::i16:
SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
break;
case MVT::i8:
if (Subtarget->is64Bit())
SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
break;
default: assert(0 && "Unknown any_extend!");
}
if (SRIdx.Val) {
SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG, NVT, N0, SRIdx);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(ResNode->dump(CurDAG));
DOUT << "\n";
Indent -= 2;
#endif
return ResNode;
} // Otherwise let generated ISel handle it.
}
break;
}
case ISD::SIGN_EXTEND_INREG: {
SDOperand N0 = Node->getOperand(0);