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AMDGPU: Fix alignment for dynamic allocas

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The alignment value also needs to be scaled by the wave size.
This commit is contained in:
Matt Arsenault 2020-05-30 11:53:54 -04:00 committed by Matt Arsenault
parent 3f75cfd780
commit 7e6b33626b
2 changed files with 8 additions and 5 deletions
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9
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -3126,9 +3126,12 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(
unsigned StackAlign = TFL->getStackAlignment();
Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
if (Align > StackAlign)
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
DAG.getConstant(-(uint64_t)Align, dl, VT));
if (Align > StackAlign) {
Tmp1 = DAG.getNode(
ISD::AND, dl, VT, Tmp1,
DAG.getConstant(-(uint64_t)Align << ST.getWavefrontSizeLog2(), dl, VT));
}
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
Tmp2 = DAG.getCALLSEQ_END(
Chain, DAG.getIntPtrConstant(0, dl, true),

4
test/CodeGen/AMDGPU/non-entry-alloca.ll
View File

@ -95,7 +95,7 @@ define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reache
; GCN-NEXT: s_cbranch_scc1 BB1_2
; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_add_i32 s6, s32, 0x1000
; GCN-NEXT: s_andn2_b32 s6, s6, 63
; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000
; GCN-NEXT: s_lshl_b32 s7, s7, 2
; GCN-NEXT: s_mov_b32 s32, s6
; GCN-NEXT: v_mov_b32_e32 v2, s6
@ -223,7 +223,7 @@ define void @func_non_entry_block_static_alloca_align64(i32 addrspace(1)* %out,
; GCN-NEXT: s_cbranch_execz BB3_2
; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_add_i32 s6, s32, 0x1000
; GCN-NEXT: s_andn2_b32 s6, s6, 63
; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000
; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: v_mov_b32_e32 v6, 1