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[AArch64] Cleanup vector-fcopysign.ll test. NFC.

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llvm-svn: 244861
This commit is contained in:
Ahmed Bougacha 2015-08-13 01:20:38 +00:00
parent 8e769a9269
commit 7e819acaaf
1 changed files with 1 additions and 13 deletions
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14
test/CodeGen/AArch64/vector-fcopysign.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple aarch64-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
@ -7,7 +7,6 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; WidenVecRes same
define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v1f32_v1f32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2s v2, #0x80, lsl #24
; CHECK-NEXT: bit.8b v0, v1, v2
; CHECK-NEXT: ret
@ -18,7 +17,6 @@ define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0
; WidenVecRes mismatched
define <1 x float> @test_copysign_v1f32_v1f64(<1 x float> %a, <1 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v1f32_v1f64:
; CHECK: ; BB#0:
; CHECK-NEXT: fcvt s1, d1
; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
; CHECK-NEXT: bit.16b v0, v1, v2
@ -35,7 +33,6 @@ declare <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b) #0
; WidenVecOp #1
define <1 x double> @test_copysign_v1f64_v1f32(<1 x double> %a, <1 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v1f64_v1f32:
; CHECK: ; BB#0:
; CHECK-NEXT: fcvt d1, s1
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: fneg.2d v2, v2
@ -48,7 +45,6 @@ define <1 x double> @test_copysign_v1f64_v1f32(<1 x double> %a, <1 x float> %b)
define <1 x double> @test_copysign_v1f64_v1f64(<1 x double> %a, <1 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v1f64_v1f64:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: fneg.2d v2, v2
; CHECK-NEXT: bit.16b v0, v1, v2
@ -63,7 +59,6 @@ declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v2f32_v2f32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2s v2, #0x80, lsl #24
; CHECK-NEXT: bit.8b v0, v1, v2
; CHECK-NEXT: ret
@ -73,7 +68,6 @@ define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0
define <2 x float> @test_copysign_v2f32_v2f64(<2 x float> %a, <2 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v2f32_v2f64:
; CHECK: ; BB#0:
; CHECK-NEXT: fcvtn v1.2s, v1.2d
; CHECK-NEXT: movi.2s v2, #0x80, lsl #24
; CHECK-NEXT: bit.8b v0, v1, v2
@ -89,7 +83,6 @@ declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0
define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v4f32_v4f32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
; CHECK-NEXT: bit.16b v0, v1, v2
; CHECK-NEXT: ret
@ -100,7 +93,6 @@ define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0
; SplitVecOp #1
define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v4f32_v4f64:
; CHECK: ; BB#0:
; CHECK-NEXT: mov s3, v0[1]
; CHECK-NEXT: mov d4, v1[1]
; CHECK-NEXT: movi.4s v5, #0x80, lsl #24
@ -130,7 +122,6 @@ declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0
define <2 x double> @test_copysign_v2f64_v232(<2 x double> %a, <2 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v2f64_v232:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: fneg.2d v2, v2
; CHECK-NEXT: fcvtl v1.2d, v1.2s
@ -143,7 +134,6 @@ define <2 x double> @test_copysign_v2f64_v232(<2 x double> %a, <2 x float> %b) #
define <2 x double> @test_copysign_v2f64_v2f64(<2 x double> %a, <2 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v2f64_v2f64:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: fneg.2d v2, v2
; CHECK-NEXT: bit.16b v0, v1, v2
@ -159,7 +149,6 @@ declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0
; SplitVecRes mismatched
define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v4f64_v4f32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d v3, #0000000000000000
; CHECK-NEXT: fcvtl2 v4.2d, v2.4s
; CHECK-NEXT: fcvtl v2.2d, v2.2s
@ -175,7 +164,6 @@ define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b)
; SplitVecRes same
define <4 x double> @test_copysign_v4f64_v4f64(<4 x double> %a, <4 x double> %b) #0 {
; CHECK-LABEL: test_copysign_v4f64_v4f64:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d v4, #0000000000000000
; CHECK-NEXT: fneg.2d v4, v4
; CHECK-NEXT: bit.16b v0, v2, v4