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[AMDGPU] Set rsrc1 flags for graphics shaders
Before they were only set for compute kernels and compute shaders but not for other shaders. Differential Revision: https://reviews.llvm.org/D89399
This commit is contained in:
Sebastian Neubauer
parent
537305eda7
commit
7ea56efeb5
@ -414,12 +414,12 @@ amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
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memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
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assert(isUInt<32>(PI.ScratchSize));
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assert(isUInt<32>(PI.ComputePGMRSrc1));
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assert(isUInt<32>(PI.getComputePGMRSrc1()));
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assert(isUInt<32>(PI.ComputePGMRSrc2));
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KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
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KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
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KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
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KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1();
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KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
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KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
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@ -1135,18 +1135,6 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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ProgInfo.MemOrdered = 1;
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}
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ProgInfo.ComputePGMRSrc1 =
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S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
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S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
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S_00B848_PRIORITY(ProgInfo.Priority) |
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S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
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S_00B848_PRIV(ProgInfo.Priv) |
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S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
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S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
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S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
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S_00B848_WGP_MODE(ProgInfo.WgpMode) |
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S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
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// 0 = X, 1 = XY, 2 = XYZ
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unsigned TIDIGCompCnt = 0;
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if (MFI->hasWorkItemIDZ())
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@ -1195,7 +1183,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
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OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1);
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OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc1);
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OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1());
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OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2);
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OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc2);
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@ -1244,12 +1232,10 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
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MD->setEntryPoint(CC, MF.getFunction().getName());
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MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
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MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
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if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
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MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
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MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC));
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if (AMDGPU::isCompute(CC)) {
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MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
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} else {
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MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
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S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
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if (CurrentProgramInfo.ScratchBlocks > 0)
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MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
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}
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@ -1293,7 +1279,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
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AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
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Out.compute_pgm_resource_registers =
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CurrentProgramInfo.ComputePGMRSrc1 |
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CurrentProgramInfo.getComputePGMRSrc1() |
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(CurrentProgramInfo.ComputePGMRSrc2 << 32);
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Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
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@ -132,6 +132,7 @@ add_llvm_target(AMDGPUCodeGen
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SIPeepholeSDWA.cpp
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SIPostRABundler.cpp
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SIPreEmitPeephole.cpp
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SIProgramInfo.cpp
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SIRegisterInfo.cpp
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SIRemoveShortExecBranches.cpp
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SIShrinkInstructions.cpp
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@ -691,16 +691,37 @@ enum DppFiMode {
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} // namespace AMDGPU
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
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#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
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#define C_00B028_MEM_ORDERED 0xFDFFFFFF
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
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#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
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#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
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#define C_00B128_MEM_ORDERED 0xF7FFFFFF
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#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
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#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
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#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
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#define C_00B228_WGP_MODE 0xF7FFFFFF
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#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
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#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
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#define C_00B228_MEM_ORDERED 0xFDFFFFFF
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#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
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#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
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#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
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#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
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#define C_00B428_WGP_MODE 0xFBFFFFFF
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#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
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#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
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#define C_00B428_MEM_ORDERED 0xFEFFFFFF
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#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
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#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
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56
lib/Target/AMDGPU/SIProgramInfo.cpp
Normal file
56
lib/Target/AMDGPU/SIProgramInfo.cpp
Normal file
@ -0,0 +1,56 @@
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//===-- SIProgramInfo.cpp ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The SIProgramInfo tracks resource usage and hardware flags for kernels and
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/// entry functions.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "SIProgramInfo.h"
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#include "SIDefines.h"
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#include "Utils/AMDGPUBaseInfo.h"
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using namespace llvm;
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uint64_t SIProgramInfo::getComputePGMRSrc1() const {
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return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
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S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
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S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
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S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) |
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S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered);
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}
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uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const {
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if (AMDGPU::isCompute(CC)) {
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return getComputePGMRSrc1();
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}
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uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
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S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
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S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
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S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode);
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switch (CC) {
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case CallingConv::AMDGPU_PS:
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Reg |= S_00B028_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_VS:
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Reg |= S_00B128_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_GS:
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Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_HS:
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Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered);
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break;
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default:
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break;
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}
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return Reg;
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}
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@ -7,7 +7,8 @@
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Defines struct to track resource usage for kernels and entry functions.
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/// Defines struct to track resource usage and hardware flags for kernels and
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/// entry functions.
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///
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//
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//===----------------------------------------------------------------------===//
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@ -15,6 +16,9 @@
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#include "llvm/IR/CallingConv.h"
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#include <cstdint>
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namespace llvm {
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/// Track resource usage for kernels / entry functions.
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@ -32,8 +36,6 @@ struct SIProgramInfo {
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uint32_t MemOrdered = 0; // GFX10+
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uint64_t ScratchSize = 0;
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uint64_t ComputePGMRSrc1 = 0;
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// Fields set in PGM_RSRC2 pm4 packet.
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uint32_t LDSBlocks = 0;
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uint32_t ScratchBlocks = 0;
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@ -64,6 +66,10 @@ struct SIProgramInfo {
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bool VCCUsed = false;
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SIProgramInfo() = default;
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/// Compute the value of the ComputePGMRsrc1 register.
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uint64_t getComputePGMRSrc1() const;
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uint64_t getPGMRSrc1(CallingConv::ID CC) const;
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};
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} // namespace llvm
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@ -12,36 +12,36 @@ define amdgpu_cs half @cs_amdpal(half %arg0) {
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}
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; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
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; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
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; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0{{$}}
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; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
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; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000{{$}}
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; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000{{$}}
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define amdgpu_es half @es_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
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; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
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; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0{{$}}
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; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
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; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000{{$}}
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; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000{{$}}
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define amdgpu_gs half @gs_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
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; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
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; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0{{$}}
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; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
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; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000{{$}}
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; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000{{$}}
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define amdgpu_hs half @hs_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
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; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
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; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0{{$}}
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; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
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; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000{{$}}
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; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000{{$}}
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define amdgpu_ls half @ls_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) {
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; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata
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; below.
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; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
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; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0{{$}}
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; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
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; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000{{$}}
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; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000{{$}}
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define amdgpu_ps half @ps_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
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; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
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; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0{{$}}
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; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
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; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000{{$}}
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; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f02c0{{$}}
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; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000{{$}}
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define amdgpu_vs half @vs_amdpal(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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@ -12,36 +12,36 @@ define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
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}
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; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
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; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
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; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0{{$}}
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; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
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; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000{{$}}
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; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c02c0{{$}}
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; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000{{$}}
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define amdgpu_es half @es_amdpal(half %arg0) #0 {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
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; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
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; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0{{$}}
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; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
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; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000{{$}}
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; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c02c0{{$}}
|
||||
; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000{{$}}
|
||||
define amdgpu_gs half @gs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c02c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000{{$}}
|
||||
define amdgpu_hs half @hs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c02c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000{{$}}
|
||||
define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
|
||||
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata
|
||||
; below.
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c02c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000{{$}}
|
||||
define amdgpu_ps half @ps_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c02c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000{{$}}
|
||||
define amdgpu_vs half @vs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
|
||||
@ -12,36 +12,36 @@ define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
|
||||
}
|
||||
|
||||
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
|
||||
; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
|
||||
; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
|
||||
; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}}
|
||||
define amdgpu_es half @es_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
|
||||
; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
|
||||
; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
|
||||
; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000{{$}}
|
||||
define amdgpu_gs half @gs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000{{$}}
|
||||
define amdgpu_hs half @hs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}}
|
||||
define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
|
||||
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata
|
||||
; below.
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000{{$}}
|
||||
define amdgpu_ps half @ps_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000{{$}}
|
||||
define amdgpu_vs half @vs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
|
||||
@ -12,36 +12,36 @@ define amdgpu_cs half @cs_amdpal(half %arg0) #0 {
|
||||
}
|
||||
|
||||
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
|
||||
; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
|
||||
; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0{{$}}
|
||||
; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}}
|
||||
define amdgpu_es half @es_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
|
||||
; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
|
||||
; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0{{$}}
|
||||
; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}}
|
||||
define amdgpu_gs half @gs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0{{$}}
|
||||
; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}}
|
||||
define amdgpu_hs half @hs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0{{$}}
|
||||
; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}}
|
||||
define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 {
|
||||
|
||||
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata
|
||||
; below.
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0{{$}}
|
||||
; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}}
|
||||
define amdgpu_ps half @ps_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0{{$}}
|
||||
; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}}
|
||||
; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf02c0{{$}}
|
||||
; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}}
|
||||
define amdgpu_vs half @vs_amdpal(half %arg0) #0 {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
|
||||
Loading…
Reference in New Issue
Block a user